[PATCH] D152790: [ARM] Fix codegen of unaligned volatile load/store of i64

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I haven't checked any hardware, but from reading the reference manuals it looked like the alignment requirement would be `Subtarget->hasV6Ops() || Subtarget->allowsUnalignedMem() ? 4 : 8`. As in for newer archs 4 is always fine. For v5te the ldrd requires an alignment of 4 with U=1 and 8 with U=0. I haven't tested that though.


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