[PATCH] D153034: [PowerPC][Future] Enable __builtin_mma_xxm[t|f]acc on PFuture

[Kamau Bridgeman via Phabricator via llvm-commits]

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The instructions xxmtacc and xxmfacc are difficult to emit using the
PFuture ISA because their register class requires an overlap of the
vector and accumulator(acc) registers which does not exist in PFuture.

PFuture ISA introduces two new instructions, dmxxinstdmr512 and
dmxxextfdmr512, which handle inserting and extracting from acc registers
better than the Power10 era instructions, xxmtacc and xxmfacc, can.
These new instructions are always produced when lowering the use of
the v512i1 (vector_quad in C) type. Since these two intrinsics take one
argument of type v512i1 a corresponding dmxx[inst|extf]dmr512
is always generated for the operand negating the need to produce the
xxm[t|f]acc. In this patch we account for this by custom lowering these
intrinsics to produce no instructions on PFuture.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153034

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll

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