[PATCH] D152937: [RISCV] Document overview of vector psuedos [nfc]

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.h:323
+  from this representation.
+  * _TU - Can represent all three policy states.  If passthrough is
+  IMPLICIT_DEF, then represents "undefined".  Otherwise, policy operand
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luke wrote:
> luke wrote:
> > Not for this patch, but should we standardise the terminology of passthrough vs. merge throughout the backend and pick one? My weak preference would be for passthrough as it’s less confusing with vmerge etc. 
> Not all TU pseudos have a policy operand (as of today). Should we document that without the policy operand it defaults to TUMU?
I think all unmasked Pseudo does not have a policy operand.

When the `merge` operand is undef, the tail policy is agnostic. When the `merge` operand is not undef, the tail policy is undisturbed.

I don't quite understand what are the instructions are affected by the default setting you have mentioned. My understanding is that at Pseudo instruction level the vector instructions all have explicit policy information. May you elaborate more?


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  https://reviews.llvm.org/D152937/new/

https://reviews.llvm.org/D152937