[PATCH] D151395: [1/3][RISCV] Define machine instruction to write an immediate into vxrm

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG56c25575ce74: [1/3][RISCV] Define machine instruction to write an immediate into vxrm (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151395/new/

https://reviews.llvm.org/D151395

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/CodeGen/RISCV/rvv/vxrm.mir


Index: llvm/test/CodeGen/RISCV/rvv/vxrm.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/vxrm.mir
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after prologepilog -o - %s | FileCheck %s --check-prefix=MIR
+# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=ASM
+
+---
+name:    verify_vxrm
+tracksRegLiveness: true
+body:     |
+  bb.0.entry:
+    liveins: $v8, $v9, $x10
+
+    ; MIR-LABEL: name: verify_vxrm
+    ; MIR: liveins: $v8, $v9, $x10
+    ; MIR-NEXT: {{  $}}
+    ; MIR-NEXT: dead $x0 = PseudoVSETVLI renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype
+    ; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm
+    ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 renamable $v8, renamable $v9, $noreg, 3 /* e8 */, implicit $vxrm, implicit $vl, implicit $vtype, implicit $vl, implicit $vtype
+    ; MIR-NEXT: PseudoRET implicit $v8
+    ; ASM-LABEL: verify_vxrm:
+    ; ASM:        # %bb.0:
+    ; ASM-NEXT:    vsetvli	zero, a0, e8, mf8, ta, ma
+    ; ASM-NEXT:    csrwi	vxrm, 0
+    ; ASM-NEXT:    vaadd.vv	v8, v8, v9
+    ; ASM-NEXT:    ret
+    %0:vr = COPY $v8
+    %1:vr = COPY $v9
+    dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype
+    WriteVXRMImm 0, implicit-def $vxrm
+    renamable $v8 = PseudoVAADD_VV_MF8 killed renamable $v8, killed renamable $v9, $noreg, 3 /* e8 */, implicit $vxrm, implicit $vl, implicit $vtype
+    PseudoRET implicit $v8
+...
Index: llvm/lib/Target/RISCV/RISCVSystemOperands.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -331,7 +331,7 @@
 //===----------------------------------------------------------------------===//
 def : SysReg<"vstart", 0x008>;
 def : SysReg<"vxsat", 0x009>;
-def : SysReg<"vxrm", 0x00A>;
+def SysRegVXRM : SysReg<"vxrm", 0x00A>;
 def : SysReg<"vcsr", 0x00F>;
 def SysRegVL : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1743,6 +1743,8 @@
 def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
 def SwapFRMImm : SwapSysRegImm<SysRegFRM, [FRM]>;
 
+def WriteVXRMImm : WriteSysRegImm<SysRegVXRM, [VXRM]>;
+
 let hasSideEffects = true in {
 def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>;
 def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>;


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