[llvm] 98153b0 - [AArch64] Fix check lines for arm64-neon-across.ll. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 15 01:25:34 PDT 2023
Author: David Green
Date: 2023-06-15T09:25:28+01:00
New Revision: 98153b088eb1e103984bdd3c5ca4b80658211e50
URL: https://github.com/llvm/llvm-project/commit/98153b088eb1e103984bdd3c5ca4b80658211e50
DIFF: https://github.com/llvm/llvm-project/commit/98153b088eb1e103984bdd3c5ca4b80658211e50.diff
LOG: [AArch64] Fix check lines for arm64-neon-across.ll. NFC
Commit de0707a2b98162ab52fa2dd9277a9bbb4f7256c7 updated the check lines, but
due to conflicting assembly not all functions kept their checks. This now
distinguishes between selection-dag and global isel.
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-neon-across.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-across.ll b/llvm/test/CodeGen/AArch64/arm64-neon-across.ll
index ed4a02bb0abfd..218f4147787d1 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-across.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-across.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
-; RUN: llc < %s -global-isel=1 -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -global-isel=1 -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
@@ -195,6 +195,17 @@ entry:
}
define i8 @test_vmaxv_s8(<8 x i8> %a) {
+; CHECK-SD-LABEL: test_vmaxv_s8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: smaxv b0, v0.8b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmaxv_s8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: smaxv b0, v0.8b
+; CHECK-GI-NEXT: smov w0, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)
%0 = trunc i32 %smaxv.i to i8
@@ -202,6 +213,17 @@ entry:
}
define i16 @test_vmaxv_s16(<4 x i16> %a) {
+; CHECK-SD-LABEL: test_vmaxv_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: smaxv h0, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmaxv_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: smaxv h0, v0.4h
+; CHECK-GI-NEXT: smov w0, v0.h[0]
+; CHECK-GI-NEXT: ret
entry:
%smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a)
%0 = trunc i32 %smaxv.i to i16
@@ -233,6 +255,17 @@ entry:
}
define i8 @test_vmaxvq_s8(<16 x i8> %a) {
+; CHECK-SD-LABEL: test_vmaxvq_s8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: smaxv b0, v0.16b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmaxvq_s8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: smaxv b0, v0.16b
+; CHECK-GI-NEXT: smov w0, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a)
%0 = trunc i32 %smaxv.i to i8
@@ -240,6 +273,17 @@ entry:
}
define i16 @test_vmaxvq_s16(<8 x i16> %a) {
+; CHECK-SD-LABEL: test_vmaxvq_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: smaxv h0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vmaxvq_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: smaxv h0, v0.8h
+; CHECK-GI-NEXT: smov w0, v0.h[0]
+; CHECK-GI-NEXT: ret
entry:
%smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a)
%0 = trunc i32 %smaxv.i to i16
@@ -293,6 +337,17 @@ entry:
}
define i8 @test_vminv_s8(<8 x i8> %a) {
+; CHECK-SD-LABEL: test_vminv_s8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sminv b0, v0.8b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vminv_s8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sminv b0, v0.8b
+; CHECK-GI-NEXT: smov w0, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a)
%0 = trunc i32 %sminv.i to i8
@@ -300,6 +355,17 @@ entry:
}
define i16 @test_vminv_s16(<4 x i16> %a) {
+; CHECK-SD-LABEL: test_vminv_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sminv h0, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vminv_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sminv h0, v0.4h
+; CHECK-GI-NEXT: smov w0, v0.h[0]
+; CHECK-GI-NEXT: ret
entry:
%sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a)
%0 = trunc i32 %sminv.i to i16
@@ -331,6 +397,17 @@ entry:
}
define i8 @test_vminvq_s8(<16 x i8> %a) {
+; CHECK-SD-LABEL: test_vminvq_s8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sminv b0, v0.16b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vminvq_s8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sminv b0, v0.16b
+; CHECK-GI-NEXT: smov w0, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a)
%0 = trunc i32 %sminv.i to i8
@@ -338,6 +415,17 @@ entry:
}
define i16 @test_vminvq_s16(<8 x i16> %a) {
+; CHECK-SD-LABEL: test_vminvq_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sminv h0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vminvq_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: sminv h0, v0.8h
+; CHECK-GI-NEXT: smov w0, v0.h[0]
+; CHECK-GI-NEXT: ret
entry:
%sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a)
%0 = trunc i32 %sminv.i to i16
@@ -391,6 +479,17 @@ entry:
}
define i8 @test_vaddv_s8(<8 x i8> %a) {
+; CHECK-SD-LABEL: test_vaddv_s8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv b0, v0.8b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vaddv_s8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv b0, v0.8b
+; CHECK-GI-NEXT: smov w0, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a)
%0 = trunc i32 %vaddv.i to i8
@@ -398,6 +497,17 @@ entry:
}
define i16 @test_vaddv_s16(<4 x i16> %a) {
+; CHECK-SD-LABEL: test_vaddv_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv h0, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vaddv_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv h0, v0.4h
+; CHECK-GI-NEXT: smov w0, v0.h[0]
+; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a)
%0 = trunc i32 %vaddv.i to i16
@@ -405,6 +515,17 @@ entry:
}
define i8 @test_vaddv_u8(<8 x i8> %a) {
+; CHECK-SD-LABEL: test_vaddv_u8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv b0, v0.8b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vaddv_u8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv b0, v0.8b
+; CHECK-GI-NEXT: smov w0, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a)
%0 = trunc i32 %vaddv.i to i8
@@ -412,6 +533,17 @@ entry:
}
define i16 @test_vaddv_u16(<4 x i16> %a) {
+; CHECK-SD-LABEL: test_vaddv_u16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv h0, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vaddv_u16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv h0, v0.4h
+; CHECK-GI-NEXT: smov w0, v0.h[0]
+; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a)
%0 = trunc i32 %vaddv.i to i16
@@ -419,6 +551,17 @@ entry:
}
define i8 @test_vaddvq_s8(<16 x i8> %a) {
+; CHECK-SD-LABEL: test_vaddvq_s8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv b0, v0.16b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vaddvq_s8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv b0, v0.16b
+; CHECK-GI-NEXT: smov w0, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a)
%0 = trunc i32 %vaddv.i to i8
@@ -426,6 +569,17 @@ entry:
}
define i16 @test_vaddvq_s16(<8 x i16> %a) {
+; CHECK-SD-LABEL: test_vaddvq_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv h0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vaddvq_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv h0, v0.8h
+; CHECK-GI-NEXT: smov w0, v0.h[0]
+; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a)
%0 = trunc i32 %vaddv.i to i16
@@ -444,6 +598,17 @@ entry:
}
define i8 @test_vaddvq_u8(<16 x i8> %a) {
+; CHECK-SD-LABEL: test_vaddvq_u8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv b0, v0.16b
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vaddvq_u8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv b0, v0.16b
+; CHECK-GI-NEXT: smov w0, v0.b[0]
+; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a)
%0 = trunc i32 %vaddv.i to i8
@@ -451,6 +616,17 @@ entry:
}
define i16 @test_vaddvq_u16(<8 x i16> %a) {
+; CHECK-SD-LABEL: test_vaddvq_u16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: addv h0, v0.8h
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: test_vaddvq_u16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: addv h0, v0.8h
+; CHECK-GI-NEXT: smov w0, v0.h[0]
+; CHECK-GI-NEXT: ret
entry:
%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a)
%0 = trunc i32 %vaddv.i to i16
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