[llvm] 61f9cb0 - [NFC] Regenerate several VE codegen tests.
Amaury Séchet via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 14 09:21:01 PDT 2023
Author: Amaury Séchet
Date: 2023-06-14T16:20:37Z
New Revision: 61f9cb002debd4b28d9d03c603df9bd428969cb6
URL: https://github.com/llvm/llvm-project/commit/61f9cb002debd4b28d9d03c603df9bd428969cb6
DIFF: https://github.com/llvm/llvm-project/commit/61f9cb002debd4b28d9d03c603df9bd428969cb6.diff
LOG: [NFC] Regenerate several VE codegen tests.
Added:
Modified:
llvm/test/CodeGen/VE/Scalar/atomic_swap.ll
llvm/test/CodeGen/VE/Scalar/br_cc.ll
llvm/test/CodeGen/VE/Scalar/brcond.ll
llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/VE/Scalar/atomic_swap.ll b/llvm/test/CodeGen/VE/Scalar/atomic_swap.ll
index f241906888356..23bb7d6efeacd 100644
--- a/llvm/test/CodeGen/VE/Scalar/atomic_swap.ll
+++ b/llvm/test/CodeGen/VE/Scalar/atomic_swap.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=ve | FileCheck %s
;;; Test atomic swap for all types and all memory order
@@ -220,7 +221,22 @@ define i64 @_Z23atomic_swap_relaxed_u64RNSt3__16atomicImEEm(ptr nocapture nonnul
; Function Attrs: nounwind mustprogress
define i128 @_Z24atomic_swap_relaxed_i128RNSt3__16atomicInEEn(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z24atomic_swap_relaxed_i128RNSt3__16atomicInEEn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB9_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
@@ -236,6 +252,9 @@ define i128 @_Z24atomic_swap_relaxed_i128RNSt3__16atomicInEEn(ptr nonnull align
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca i128, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3)
@@ -251,7 +270,22 @@ define i128 @_Z24atomic_swap_relaxed_i128RNSt3__16atomicInEEn(ptr nonnull align
; Function Attrs: nounwind mustprogress
define i128 @_Z24atomic_swap_relaxed_u128RNSt3__16atomicIoEEo(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z24atomic_swap_relaxed_u128RNSt3__16atomicIoEEo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB10_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
@@ -267,6 +301,9 @@ define i128 @_Z24atomic_swap_relaxed_u128RNSt3__16atomicIoEEo(ptr nonnull align
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca i128, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3)
@@ -432,7 +469,22 @@ define i64 @_Z23atomic_swap_acquire_u64RNSt3__16atomicImEEm(ptr nocapture nonnul
; Function Attrs: nounwind mustprogress
define i128 @_Z24atomic_swap_acquire_i128RNSt3__16atomicInEEn(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z24atomic_swap_acquire_i128RNSt3__16atomicInEEn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB20_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB20_2:
; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
@@ -448,6 +500,9 @@ define i128 @_Z24atomic_swap_acquire_i128RNSt3__16atomicInEEn(ptr nonnull align
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca i128, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3)
@@ -463,7 +518,22 @@ define i128 @_Z24atomic_swap_acquire_i128RNSt3__16atomicInEEn(ptr nonnull align
; Function Attrs: nounwind mustprogress
define i128 @_Z24atomic_swap_acquire_u128RNSt3__16atomicIoEEo(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z24atomic_swap_acquire_u128RNSt3__16atomicIoEEo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB21_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB21_2:
; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
@@ -479,6 +549,9 @@ define i128 @_Z24atomic_swap_acquire_u128RNSt3__16atomicIoEEo(ptr nonnull align
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca i128, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3)
@@ -653,7 +726,22 @@ define i64 @_Z23atomic_swap_seq_cst_u64RNSt3__16atomicImEEm(ptr nocapture nonnul
; Function Attrs: nounwind mustprogress
define i128 @_Z24atomic_swap_seq_cst_i128RNSt3__16atomicInEEn(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z24atomic_swap_seq_cst_i128RNSt3__16atomicInEEn:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB31_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
@@ -669,6 +757,9 @@ define i128 @_Z24atomic_swap_seq_cst_i128RNSt3__16atomicInEEn(ptr nonnull align
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca i128, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3)
@@ -684,7 +775,22 @@ define i128 @_Z24atomic_swap_seq_cst_i128RNSt3__16atomicInEEn(ptr nonnull align
; Function Attrs: nounwind mustprogress
define i128 @_Z24atomic_swap_seq_cst_u128RNSt3__16atomicIoEEo(ptr nonnull align 16 dereferenceable(16) %0, i128 %1) {
; CHECK-LABEL: _Z24atomic_swap_seq_cst_u128RNSt3__16atomicIoEEo:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB32_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: or %s5, 0, %s0
; CHECK-NEXT: st %s2, 264(, %s11)
; CHECK-NEXT: st %s1, 256(, %s11)
@@ -700,6 +806,9 @@ define i128 @_Z24atomic_swap_seq_cst_u128RNSt3__16atomicIoEEo(ptr nonnull align
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%3 = alloca i128, align 16
%4 = alloca i128, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %3)
@@ -715,7 +824,19 @@ define i128 @_Z24atomic_swap_seq_cst_u128RNSt3__16atomicIoEEo(ptr nonnull align
; Function Attrs: nofree nounwind mustprogress
define zeroext i1 @_Z26atomic_swap_relaxed_stk_i1b(i1 zeroext %0) {
; CHECK-LABEL: _Z26atomic_swap_relaxed_stk_i1b:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB33_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s1, 1, (0)1
; CHECK-NEXT: lea %s2, 8(, %s11)
@@ -742,7 +863,19 @@ declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
; Function Attrs: nofree nounwind mustprogress
define signext i8 @_Z26atomic_swap_relaxed_stk_i8c(i8 signext %0) {
; CHECK-LABEL: _Z26atomic_swap_relaxed_stk_i8c:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB34_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s1, 1, (0)1
; CHECK-NEXT: lea %s2, 8(, %s11)
@@ -761,7 +894,19 @@ define signext i8 @_Z26atomic_swap_relaxed_stk_i8c(i8 signext %0) {
; Function Attrs: nofree nounwind mustprogress
define zeroext i8 @_Z26atomic_swap_relaxed_stk_u8h(i8 zeroext %0) {
; CHECK-LABEL: _Z26atomic_swap_relaxed_stk_u8h:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB35_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB35_2:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s1, 1, (0)1
; CHECK-NEXT: lea %s2, 8(, %s11)
@@ -779,7 +924,19 @@ define zeroext i8 @_Z26atomic_swap_relaxed_stk_u8h(i8 zeroext %0) {
; Function Attrs: nofree nounwind mustprogress
define signext i16 @_Z27atomic_swap_relaxed_stk_i16s(i16 signext %0) {
; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_i16s:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB36_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB36_2:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s1, 3, (0)1
; CHECK-NEXT: lea %s2, 8(, %s11)
@@ -798,7 +955,19 @@ define signext i16 @_Z27atomic_swap_relaxed_stk_i16s(i16 signext %0) {
; Function Attrs: nofree nounwind mustprogress
define zeroext i16 @_Z27atomic_swap_relaxed_stk_u16t(i16 zeroext %0) {
; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_u16t:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB37_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s1, 3, (0)1
; CHECK-NEXT: lea %s2, 8(, %s11)
@@ -816,7 +985,19 @@ define zeroext i16 @_Z27atomic_swap_relaxed_stk_u16t(i16 zeroext %0) {
; Function Attrs: nofree nounwind mustprogress
define signext i32 @_Z27atomic_swap_relaxed_stk_i32i(i32 signext %0) {
; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_i32i:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB38_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB38_2:
; CHECK-NEXT: ts1am.w %s0, 8(%s11), 15
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
@@ -831,7 +1012,19 @@ define signext i32 @_Z27atomic_swap_relaxed_stk_i32i(i32 signext %0) {
; Function Attrs: nofree nounwind mustprogress
define zeroext i32 @_Z27atomic_swap_relaxed_stk_u32j(i32 zeroext %0) {
; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_u32j:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB39_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB39_2:
; CHECK-NEXT: ts1am.w %s0, 8(%s11), 15
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: adds.l %s11, 16, %s11
@@ -846,7 +1039,19 @@ define zeroext i32 @_Z27atomic_swap_relaxed_stk_u32j(i32 zeroext %0) {
; Function Attrs: nofree nounwind mustprogress
define i64 @_Z27atomic_swap_relaxed_stk_i64l(i64 %0) {
; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_i64l:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB40_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB40_2:
; CHECK-NEXT: lea %s1, 255
; CHECK-NEXT: ts1am.l %s0, 8(%s11), %s1
; CHECK-NEXT: adds.l %s11, 16, %s11
@@ -861,7 +1066,19 @@ define i64 @_Z27atomic_swap_relaxed_stk_i64l(i64 %0) {
; Function Attrs: nofree nounwind mustprogress
define i64 @_Z27atomic_swap_relaxed_stk_u64m(i64 %0) {
; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_u64m:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.l %s11, -16, %s11
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB41_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB41_2:
; CHECK-NEXT: lea %s1, 255
; CHECK-NEXT: ts1am.l %s0, 8(%s11), %s1
; CHECK-NEXT: adds.l %s11, 16, %s11
@@ -876,7 +1093,22 @@ define i64 @_Z27atomic_swap_relaxed_stk_u64m(i64 %0) {
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_swap_relaxed_stk_i128n(i128 %0) {
; CHECK-LABEL: _Z28atomic_swap_relaxed_stk_i128n:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -288(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB42_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB42_2:
; CHECK-NEXT: st %s1, 280(, %s11)
; CHECK-NEXT: st %s0, 272(, %s11)
; CHECK-NEXT: lea %s0, __atomic_exchange at lo
@@ -891,6 +1123,9 @@ define i128 @_Z28atomic_swap_relaxed_stk_i128n(i128 %0) {
; CHECK-NEXT: ld %s1, 264(, %s11)
; CHECK-NEXT: ld %s0, 256(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%2 = alloca i128, align 16
%3 = alloca i128, align 16
%4 = alloca %"struct.std::__1::atomic.40", align 16
@@ -909,7 +1144,22 @@ define i128 @_Z28atomic_swap_relaxed_stk_i128n(i128 %0) {
; Function Attrs: nounwind mustprogress
define i128 @_Z28atomic_swap_relaxed_stk_u128o(i128 %0) {
; CHECK-LABEL: _Z28atomic_swap_relaxed_stk_u128o:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -288(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB43_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB43_2:
; CHECK-NEXT: st %s1, 280(, %s11)
; CHECK-NEXT: st %s0, 272(, %s11)
; CHECK-NEXT: lea %s0, __atomic_exchange at lo
@@ -924,6 +1174,9 @@ define i128 @_Z28atomic_swap_relaxed_stk_u128o(i128 %0) {
; CHECK-NEXT: ld %s1, 264(, %s11)
; CHECK-NEXT: ld %s0, 256(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%2 = alloca i128, align 16
%3 = alloca i128, align 16
%4 = alloca %"struct.std::__1::atomic.45", align 16
@@ -1108,7 +1361,22 @@ define i64 @_Z26atomic_swap_relaxed_gv_u64m(i64 %0) {
; Function Attrs: nounwind mustprogress
define i128 @_Z27atomic_swap_relaxed_gv_i128n(i128 %0) {
; CHECK-LABEL: _Z27atomic_swap_relaxed_gv_i128n:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB53_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB53_2:
; CHECK-NEXT: st %s1, 264(, %s11)
; CHECK-NEXT: st %s0, 256(, %s11)
; CHECK-NEXT: lea %s0, __atomic_exchange at lo
@@ -1125,6 +1393,9 @@ define i128 @_Z27atomic_swap_relaxed_gv_i128n(i128 %0) {
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%2 = alloca i128, align 16
%3 = alloca i128, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2)
@@ -1140,7 +1411,22 @@ define i128 @_Z27atomic_swap_relaxed_gv_i128n(i128 %0) {
; Function Attrs: nounwind mustprogress
define i128 @_Z27atomic_swap_relaxed_gv_u128o(i128 %0) {
; CHECK-LABEL: _Z27atomic_swap_relaxed_gv_u128o:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -272(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB54_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB54_2:
; CHECK-NEXT: st %s1, 264(, %s11)
; CHECK-NEXT: st %s0, 256(, %s11)
; CHECK-NEXT: lea %s0, __atomic_exchange at lo
@@ -1157,6 +1443,9 @@ define i128 @_Z27atomic_swap_relaxed_gv_u128o(i128 %0) {
; CHECK-NEXT: ld %s1, 248(, %s11)
; CHECK-NEXT: ld %s0, 240(, %s11)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%2 = alloca i128, align 16
%3 = alloca i128, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %2)
diff --git a/llvm/test/CodeGen/VE/Scalar/br_cc.ll b/llvm/test/CodeGen/VE/Scalar/br_cc.ll
index 92cb941b0983c..34d2c891fd7b0 100644
--- a/llvm/test/CodeGen/VE/Scalar/br_cc.ll
+++ b/llvm/test/CodeGen/VE/Scalar/br_cc.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=ve | FileCheck %s
; Function Attrs: nounwind
@@ -5,12 +6,12 @@ define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) {
; CHECK-LABEL: br_cc_i1_var:
; CHECK: # %bb.0:
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s0, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = xor i1 %0, %1
br i1 %3, label %5, label %4
@@ -27,12 +28,12 @@ define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) {
define void @br_cc_i8_var(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: br_cc_i8_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w %s0, %s1, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1
br i1 %3, label %4, label %5
@@ -49,12 +50,12 @@ define void @br_cc_i8_var(i8 signext %0, i8 signext %1) {
define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: br_cc_u8_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w %s0, %s1, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i8 %0, %1
br i1 %3, label %4, label %5
@@ -71,12 +72,12 @@ define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) {
define void @br_cc_i16_var(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: br_cc_i16_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w %s0, %s1, .LBB3_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1
br i1 %3, label %4, label %5
@@ -93,12 +94,12 @@ define void @br_cc_i16_var(i16 signext %0, i16 signext %1) {
define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: br_cc_u16_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w %s0, %s1, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i16 %0, %1
br i1 %3, label %4, label %5
@@ -115,12 +116,12 @@ define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) {
define void @br_cc_i32_var(i32 signext %0, i32 signext %1) {
; CHECK-LABEL: br_cc_i32_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w %s0, %s1, .LBB5_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1
br i1 %3, label %4, label %5
@@ -137,12 +138,12 @@ define void @br_cc_i32_var(i32 signext %0, i32 signext %1) {
define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) {
; CHECK-LABEL: br_cc_u32_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w %s0, %s1, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i32 %0, %1
br i1 %3, label %4, label %5
@@ -159,12 +160,12 @@ define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) {
define void @br_cc_i64_var(i64 %0, i64 %1) {
; CHECK-LABEL: br_cc_i64_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.l %s0, %s1, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1
br i1 %3, label %4, label %5
@@ -181,12 +182,12 @@ define void @br_cc_i64_var(i64 %0, i64 %1) {
define void @br_cc_u64_var(i64 %0, i64 %1) {
; CHECK-LABEL: br_cc_u64_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.l %s0, %s1, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i64 %0, %1
br i1 %3, label %4, label %5
@@ -206,12 +207,12 @@ define void @br_cc_i128_var(i128 %0, i128 %1) {
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: brne.l 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.l 0, %s0, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1
br i1 %3, label %4, label %5
@@ -231,12 +232,12 @@ define void @br_cc_u128_var(i128 %0, i128 %1) {
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: brne.l 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.l 0, %s0, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp eq i128 %0, %1
br i1 %3, label %4, label %5
@@ -253,12 +254,12 @@ define void @br_cc_u128_var(i128 %0, i128 %1) {
define void @br_cc_float_var(float %0, float %1) {
; CHECK-LABEL: br_cc_float_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.s %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.s %s0, %s1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq float %0, %1
br i1 %3, label %4, label %5
@@ -275,12 +276,12 @@ define void @br_cc_float_var(float %0, float %1) {
define void @br_cc_double_var(double %0, double %1) {
; CHECK-LABEL: br_cc_double_var:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.d %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.d %s0, %s1, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq double %0, %1
br i1 %3, label %4, label %5
@@ -298,12 +299,12 @@ define void @br_cc_quad_var(fp128 %0, fp128 %1) {
; CHECK-LABEL: br_cc_quad_var:
; CHECK: # %bb.0:
; CHECK-NEXT: fcmp.q %s0, %s2, %s0
-; CHECK-NEXT: brne.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.d 0, %s0, .LBB13_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB13_2:
; CHECK-NEXT: b.l.t (, %s10)
%3 = fcmp fast oeq fp128 %0, %1
br i1 %3, label %4, label %5
@@ -320,12 +321,12 @@ define void @br_cc_quad_var(fp128 %0, fp128 %1) {
define void @br_cc_i1_imm(i1 zeroext %0) {
; CHECK-LABEL: br_cc_i1_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s0, .LBB14_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB14_2:
; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %3, label %2
@@ -341,12 +342,12 @@ define void @br_cc_i1_imm(i1 zeroext %0) {
define void @br_cc_i8_imm(i8 signext %0) {
; CHECK-LABEL: br_cc_i8_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: brlt.w -10, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.w -10, %s0, .LBB15_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB15_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i8 %0, -9
br i1 %2, label %3, label %4
@@ -364,12 +365,12 @@ define void @br_cc_u8_imm(i8 zeroext %0) {
; CHECK-LABEL: br_cc_u8_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 8, %s0
-; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.w 0, %s0, .LBB16_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB16_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i8 %0, 9
br i1 %2, label %3, label %4
@@ -386,12 +387,12 @@ define void @br_cc_u8_imm(i8 zeroext %0) {
define void @br_cc_i16_imm(i16 signext %0) {
; CHECK-LABEL: br_cc_i16_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: brlt.w 62, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.w 62, %s0, .LBB17_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB17_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i16 %0, 63
br i1 %2, label %3, label %4
@@ -409,12 +410,12 @@ define void @br_cc_u16_imm(i16 zeroext %0) {
; CHECK-LABEL: br_cc_u16_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 63, %s0
-; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.w 0, %s0, .LBB18_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB18_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i16 %0, 64
br i1 %2, label %3, label %4
@@ -431,12 +432,12 @@ define void @br_cc_u16_imm(i16 zeroext %0) {
define void @br_cc_i32_imm(i32 signext %0) {
; CHECK-LABEL: br_cc_i32_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: brlt.w 63, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.w 63, %s0, .LBB19_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB19_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i32 %0, 64
br i1 %2, label %3, label %4
@@ -454,12 +455,12 @@ define void @br_cc_u32_imm(i32 zeroext %0) {
; CHECK-LABEL: br_cc_u32_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 63, %s0
-; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.w 0, %s0, .LBB20_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB20_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i32 %0, 64
br i1 %2, label %3, label %4
@@ -476,12 +477,12 @@ define void @br_cc_u32_imm(i32 zeroext %0) {
define void @br_cc_i64_imm(i64 %0) {
; CHECK-LABEL: br_cc_i64_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: brlt.l 63, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.l 63, %s0, .LBB21_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB21_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i64 %0, 64
br i1 %2, label %3, label %4
@@ -499,12 +500,12 @@ define void @br_cc_u64_imm(i64 %0) {
; CHECK-LABEL: br_cc_u64_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, 63, %s0
-; CHECK-NEXT: brgt.l 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.l 0, %s0, .LBB22_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB22_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i64 %0, 64
br i1 %2, label %3, label %4
@@ -528,12 +529,12 @@ define void @br_cc_i128_imm(i128 %0) {
; CHECK-NEXT: cmpu.l %s0, %s0, (58)0
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s1
-; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s4, .LBB23_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB23_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp slt i128 %0, 64
br i1 %2, label %3, label %4
@@ -557,12 +558,12 @@ define void @br_cc_u128_imm(i128 %0) {
; CHECK-NEXT: cmpu.l %s0, %s0, (58)0
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s1
-; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s4, .LBB24_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB24_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ult i128 %0, 64
br i1 %2, label %3, label %4
@@ -579,12 +580,12 @@ define void @br_cc_u128_imm(i128 %0) {
define void @br_cc_float_imm(float %0) {
; CHECK-LABEL: br_cc_float_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: brle.s 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brle.s 0, %s0, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt float %0, 0.000000e+00
br i1 %2, label %3, label %4
@@ -601,12 +602,12 @@ define void @br_cc_float_imm(float %0) {
define void @br_cc_double_imm(double %0) {
; CHECK-LABEL: br_cc_double_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: brle.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brle.d 0, %s0, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt double %0, 0.000000e+00
br i1 %2, label %3, label %4
@@ -623,18 +624,18 @@ define void @br_cc_double_imm(double %0) {
define void @br_cc_quad_imm(fp128 %0) {
; CHECK-LABEL: br_cc_quad_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0 at lo
+; CHECK-NEXT: lea %s2, .LCPI27_0 at lo
; CHECK-NEXT: and %s2, %s2, (32)0
-; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0 at hi(, %s2)
+; CHECK-NEXT: lea.sl %s2, .LCPI27_0 at hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fcmp.q %s0, %s4, %s0
-; CHECK-NEXT: brge.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brge.d 0, %s0, .LBB27_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast olt fp128 %0, 0xL00000000000000000000000000000000
br i1 %2, label %3, label %4
@@ -651,12 +652,12 @@ define void @br_cc_quad_imm(fp128 %0) {
define void @br_cc_imm_i1(i1 zeroext %0) {
; CHECK-LABEL: br_cc_imm_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w 0, %s0, .LBB28_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB28_2:
; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %2, label %3
@@ -672,12 +673,12 @@ define void @br_cc_imm_i1(i1 zeroext %0) {
define void @br_cc_imm_i8(i8 signext %0) {
; CHECK-LABEL: br_cc_imm_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: brgt.w -9, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.w -9, %s0, .LBB29_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB29_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i8 %0, -10
br i1 %2, label %3, label %4
@@ -695,12 +696,12 @@ define void @br_cc_imm_u8(i8 zeroext %0) {
; CHECK-LABEL: br_cc_imm_u8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, 9, %s0
-; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.w 0, %s0, .LBB30_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB30_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i8 %0, 8
br i1 %2, label %3, label %4
@@ -717,12 +718,12 @@ define void @br_cc_imm_u8(i8 zeroext %0) {
define void @br_cc_imm_i16(i16 signext %0) {
; CHECK-LABEL: br_cc_imm_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: brgt.w 63, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.w 63, %s0, .LBB31_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i16 %0, 62
br i1 %2, label %3, label %4
@@ -741,12 +742,12 @@ define void @br_cc_imm_u16(i16 zeroext %0) {
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 64
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
-; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.w 0, %s0, .LBB32_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i16 %0, 63
br i1 %2, label %3, label %4
@@ -763,12 +764,12 @@ define void @br_cc_imm_u16(i16 zeroext %0) {
define void @br_cc_imm_i32(i32 signext %0) {
; CHECK-LABEL: br_cc_imm_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: brgt.w -64, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.w -64, %s0, .LBB33_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i32 %0, -65
br i1 %2, label %3, label %4
@@ -786,12 +787,12 @@ define void @br_cc_imm_u32(i32 zeroext %0) {
; CHECK-LABEL: br_cc_imm_u32:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s0, -64, %s0
-; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.w 0, %s0, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i32 %0, -65
br i1 %2, label %3, label %4
@@ -808,12 +809,12 @@ define void @br_cc_imm_u32(i32 zeroext %0) {
define void @br_cc_imm_i64(i64 %0) {
; CHECK-LABEL: br_cc_imm_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: brgt.l -64, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.l -64, %s0, .LBB35_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB35_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i64 %0, -65
br i1 %2, label %3, label %4
@@ -831,12 +832,12 @@ define void @br_cc_imm_u64(i64 %0) {
; CHECK-LABEL: br_cc_imm_u64:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s0, -64, %s0
-; CHECK-NEXT: brlt.l 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.l 0, %s0, .LBB36_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB36_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i64 %0, -65
br i1 %2, label %3, label %4
@@ -861,12 +862,12 @@ define void @br_cc_imm_i128(i128 %0) {
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: cmpu.l %s0, %s1, (0)0
; CHECK-NEXT: cmov.l.eq %s4, %s3, %s0
-; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s4, .LBB37_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp sgt i128 %0, -65
br i1 %2, label %3, label %4
@@ -891,12 +892,12 @@ define void @br_cc_imm_u128(i128 %0) {
; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
; CHECK-NEXT: cmpu.l %s0, %s1, (0)0
; CHECK-NEXT: cmov.l.eq %s4, %s3, %s0
-; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s4, .LBB38_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB38_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = icmp ugt i128 %0, -65
br i1 %2, label %3, label %4
@@ -913,12 +914,12 @@ define void @br_cc_imm_u128(i128 %0) {
define void @br_cc_imm_float(float %0) {
; CHECK-LABEL: br_cc_imm_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: brgt.s 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.s 0, %s0, .LBB39_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB39_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult float %0, 0.000000e+00
br i1 %2, label %4, label %3
@@ -935,12 +936,12 @@ define void @br_cc_imm_float(float %0) {
define void @br_cc_imm_double(double %0) {
; CHECK-LABEL: br_cc_imm_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: brgt.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brgt.d 0, %s0, .LBB40_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB40_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult double %0, 0.000000e+00
br i1 %2, label %4, label %3
@@ -957,18 +958,18 @@ define void @br_cc_imm_double(double %0) {
define void @br_cc_imm_quad(fp128 %0) {
; CHECK-LABEL: br_cc_imm_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0 at lo
+; CHECK-NEXT: lea %s2, .LCPI41_0 at lo
; CHECK-NEXT: and %s2, %s2, (32)0
-; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0 at hi(, %s2)
+; CHECK-NEXT: lea.sl %s2, .LCPI41_0 at hi(, %s2)
; CHECK-NEXT: ld %s4, 8(, %s2)
; CHECK-NEXT: ld %s5, (, %s2)
; CHECK-NEXT: fcmp.q %s0, %s4, %s0
-; CHECK-NEXT: brlt.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brlt.d 0, %s0, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB41_2:
; CHECK-NEXT: b.l.t (, %s10)
%2 = fcmp fast ult fp128 %0, 0xL00000000000000000000000000000000
br i1 %2, label %4, label %3
diff --git a/llvm/test/CodeGen/VE/Scalar/brcond.ll b/llvm/test/CodeGen/VE/Scalar/brcond.ll
index d5209bf825052..45ac45ee4f082 100644
--- a/llvm/test/CodeGen/VE/Scalar/brcond.ll
+++ b/llvm/test/CodeGen/VE/Scalar/brcond.ll
@@ -1,15 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=ve | FileCheck %s
; Function Attrs: nounwind
define void @brcond_then(i1 zeroext %0) {
; CHECK-LABEL: brcond_then:
; CHECK: # %bb.0:
-; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: breq.w 0, %s0, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %2, label %3
@@ -25,12 +26,12 @@ define void @brcond_then(i1 zeroext %0) {
define void @brcond_else(i1 zeroext %0) {
; CHECK-LABEL: brcond_else:
; CHECK: # %bb.0:
-; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: brne.w 0, %s0, .LBB1_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: b.l.t (, %s10)
br i1 %0, label %3, label %2
diff --git a/llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll b/llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll
index 1e708f2b0649a..4e30778d5c158 100644
--- a/llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll
+++ b/llvm/test/CodeGen/VE/Scalar/fp_extload_truncstore.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
declare i16 @llvm.convert.to.fp16.f32(float %a)
@@ -8,13 +9,31 @@ declare double @llvm.convert.from.fp16.f64(i16 %a)
define float @func_i16fp32(ptr %a) {
; CHECK-LABEL: func_i16fp32:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -240(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB0_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: lea %s1, __gnu_h2f_ieee at lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee at hi(, %s1)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%a.val = load i16, ptr %a, align 4
%a.asd = call float @llvm.convert.from.fp16.f32(i16 %a.val)
ret float %a.asd
@@ -22,7 +41,22 @@ define float @func_i16fp32(ptr %a) {
define double @func_i16fp64(ptr %a) {
; CHECK-LABEL: func_i16fp64:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -240(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: lea %s1, __gnu_h2f_ieee at lo
; CHECK-NEXT: and %s1, %s1, (32)0
@@ -30,6 +64,9 @@ define double @func_i16fp64(ptr %a) {
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%a.val = load i16, ptr %a, align 4
%a.asd = call double @llvm.convert.from.fp16.f64(i16 %a.val)
ret double %a.asd
@@ -37,13 +74,31 @@ define double @func_i16fp64(ptr %a) {
define float @func_fp16fp32(ptr %a) {
; CHECK-LABEL: func_fp16fp32:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -240(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: lea %s1, __gnu_h2f_ieee at lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s12, __gnu_h2f_ieee at hi(, %s1)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%a.val = load half, ptr %a, align 4
%a.asd = fpext half %a.val to float
ret float %a.asd
@@ -51,7 +106,22 @@ define float @func_fp16fp32(ptr %a) {
define double @func_fp16fp64(ptr %a) {
; CHECK-LABEL: func_fp16fp64:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -240(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB3_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: ld2b.zx %s0, (, %s0)
; CHECK-NEXT: lea %s1, __gnu_h2f_ieee at lo
; CHECK-NEXT: and %s1, %s1, (32)0
@@ -59,6 +129,9 @@ define double @func_fp16fp64(ptr %a) {
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%a.val = load half, ptr %a, align 4
%a.asd = fpext half %a.val to double
ret double %a.asd
@@ -66,7 +139,22 @@ define double @func_fp16fp64(ptr %a) {
define void @func_fp32i16(ptr %fl.ptr, float %val) {
; CHECK-LABEL: func_fp32i16:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -240(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB4_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __gnu_f2h_ieee at lo
@@ -77,6 +165,9 @@ define void @func_fp32i16(ptr %fl.ptr, float %val) {
; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%val.asf = call i16 @llvm.convert.to.fp16.f32(float %val)
store i16 %val.asf, ptr %fl.ptr
ret void
@@ -84,7 +175,22 @@ define void @func_fp32i16(ptr %fl.ptr, float %val) {
define half @func_fp32fp16(ptr %fl.ptr, float %a) {
; CHECK-LABEL: func_fp32fp16:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -240(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB5_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: st %s19, 296(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0
@@ -103,6 +209,9 @@ define half @func_fp32fp16(ptr %fl.ptr, float %a) {
; CHECK-NEXT: ld %s19, 296(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%a.asd = fptrunc float %a to half
store half %a.asd, ptr %fl.ptr
ret half %a.asd
@@ -121,7 +230,22 @@ define double @func_fp32fp64(ptr %a) {
define void @func_fp64i16(ptr %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64i16:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -240(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB7_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __truncdfhf2 at lo
@@ -132,6 +256,9 @@ define void @func_fp64i16(ptr %fl.ptr, double %val) {
; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%val.asf = call i16 @llvm.convert.to.fp16.f64(double %val)
store i16 %val.asf, ptr %fl.ptr
ret void
@@ -139,7 +266,22 @@ define void @func_fp64i16(ptr %fl.ptr, double %val) {
define void @func_fp64fp16(ptr %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64fp16:
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: st %s9, (, %s11)
+; CHECK-NEXT: st %s10, 8(, %s11)
+; CHECK-NEXT: or %s9, 0, %s11
+; CHECK-NEXT: lea %s11, -240(, %s11)
+; CHECK-NEXT: brge.l.t %s11, %s8, .LBB8_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ld %s61, 24(, %s14)
+; CHECK-NEXT: or %s62, 0, %s0
+; CHECK-NEXT: lea %s63, 315
+; CHECK-NEXT: shm.l %s63, (%s61)
+; CHECK-NEXT: shm.l %s8, 8(%s61)
+; CHECK-NEXT: shm.l %s11, 16(%s61)
+; CHECK-NEXT: monc
+; CHECK-NEXT: or %s0, 0, %s62
+; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: st %s18, 288(, %s11) # 8-byte Folded Spill
; CHECK-NEXT: or %s18, 0, %s0
; CHECK-NEXT: lea %s0, __truncdfhf2 at lo
@@ -150,6 +292,9 @@ define void @func_fp64fp16(ptr %fl.ptr, double %val) {
; CHECK-NEXT: st2b %s0, (, %s18)
; CHECK-NEXT: ld %s18, 288(, %s11) # 8-byte Folded Reload
; CHECK-NEXT: or %s11, 0, %s9
+; CHECK-NEXT: ld %s10, 8(, %s11)
+; CHECK-NEXT: ld %s9, (, %s11)
+; CHECK-NEXT: b.l.t (, %s10)
%val.asf = fptrunc double %val to half
store half %val.asf, ptr %fl.ptr
ret void
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