[PATCH] D152844: [RISCV][InsertVSETVLI] Rework code structure to make reasoning about undefined lanes explicit [NFC]

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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We already have several places in this code which reason about whether the inactive lanes are defined, and are about to add one more in D151653 <https://reviews.llvm.org/D151653>.  Let's go ahead and common the code so that we don't have the same concept repeating in multiply places.

Asking for review mostly because of the change to computeInfoForInstr.  I want a second pair of eyes confirming I'm not missing something there.  (All of the removed asserts are covered by the verifier; I checked.)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152844

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

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