[PATCH] D152826: [AArch64] Improve shuffles of i1 vectors (WIP)

[Ricardo Jesus via Phabricator via llvm-commits]

rjj created this revision.
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If the operands of a shuffle are concatenations of i1 vectors and undef,
this patch tries to rewrite the operands without the concatenation by doing a
bitcast instead. This avoids BUILD_VECTORs during legalisation, which
ultimately leads to better codegen.

This is WIP because currently two tests are failing that need looking into, but
in the meantime I wanted to get your opinion @dmgreen  on the approach.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152826

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/aarch64-shuffle-of-i1s.ll

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