[llvm] 0662167 - [GlobalIsel][X86] Update legalization of G_PTR_ADD
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 9 05:27:46 PDT 2023
Author: Simon Pilgrim
Date: 2023-06-09T13:27:25+01:00
New Revision: 0662167c5b1ff45354e7c80e1495293bb8c6cf2b
URL: https://github.com/llvm/llvm-project/commit/0662167c5b1ff45354e7c80e1495293bb8c6cf2b
DIFF: https://github.com/llvm/llvm-project/commit/0662167c5b1ff45354e7c80e1495293bb8c6cf2b.diff
LOG: [GlobalIsel][X86] Update legalization of G_PTR_ADD
Replace the legacy legalizer versions
Add test coverage for 32-bit targets and non-constant ptr offsets
Added:
Modified:
llvm/lib/Target/X86/X86LegalizerInfo.cpp
llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
index 9b8b84a66462f..325b7b6fad841 100644
--- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -278,6 +278,14 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, sMaxScalar}});
+ getActionDefinitionsBuilder(G_PTR_ADD)
+ .legalIf([=](const LegalityQuery &Query) -> bool {
+ return typePairInSet(0, 1, {{p0, s32}})(Query) ||
+ (Is64Bit && typePairInSet(0, 1, {{p0, s64}})(Query));
+ })
+ .widenScalarToNextPow2(1, /*Min*/ 32)
+ .clampScalar(1, s32, sMaxScalar);
+
// sext, zext, and anyext
getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
.legalIf([=](const LegalityQuery &Query) {
@@ -353,9 +361,6 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
for (unsigned MemOp : {G_LOAD, G_STORE})
LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(
MemOp, 0, LegacyLegalizerInfo::narrowToSmallerAndWidenToSmallest);
- LegacyInfo.setLegalizeScalarToDifferentSizeStrategy(
- G_PTR_ADD, 1,
- LegacyLegalizerInfo::widenToLargerTypesUnsupportedOtherwise);
LegacyInfo.computeTables();
verify(*STI.getInstrInfo());
@@ -397,9 +402,6 @@ void X86LegalizerInfo::setLegalizerInfo32bit() {
LegacyInfo.setAction({G_FRAME_INDEX, p0}, LegacyLegalizeActions::Legal);
LegacyInfo.setAction({G_GLOBAL_VALUE, p0}, LegacyLegalizeActions::Legal);
- LegacyInfo.setAction({G_PTR_ADD, p0}, LegacyLegalizeActions::Legal);
- LegacyInfo.setAction({G_PTR_ADD, 1, s32}, LegacyLegalizeActions::Legal);
-
// Control-flow
LegacyInfo.setAction({G_BRCOND, s1}, LegacyLegalizeActions::Legal);
@@ -432,9 +434,6 @@ void X86LegalizerInfo::setLegalizerInfo64bit() {
for (unsigned MemOp : {G_LOAD, G_STORE})
LegacyInfo.setAction({MemOp, s64}, LegacyLegalizeActions::Legal);
- // Pointer-handling
- LegacyInfo.setAction({G_PTR_ADD, 1, s64}, LegacyLegalizeActions::Legal);
-
getActionDefinitionsBuilder(G_SITOFP)
.legalForCartesianProduct({s32, s64})
.clampScalar(1, s32, s64)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
index 77ed64a29b896..b1beb2e98cc8d 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
@@ -1,26 +1,64 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
+# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86
--- |
- define void @test_gep_i8(ptr %addr) {
+ define void @test_gep_i8c(ptr %addr) {
%arrayidx = getelementptr i32, ptr undef, i8 5
ret void
}
+ define void @test_gep_i8(ptr %addr, i8 %ofs) {
+ %arrayidx = getelementptr i32, ptr undef, i8 %ofs
+ ret void
+ }
- define void @test_gep_i16(ptr %addr) {
+ define void @test_gep_i16c(ptr %addr) {
%arrayidx = getelementptr i32, ptr undef, i16 5
ret void
}
+ define void @test_gep_i16(ptr %addr, i16 %ofs) {
+ %arrayidx = getelementptr i32, ptr undef, i16 %ofs
+ ret void
+ }
- define void @test_gep_i32(ptr %addr) {
+ define void @test_gep_i32c(ptr %addr) {
%arrayidx = getelementptr i32, ptr undef, i32 5
ret void
}
+ define void @test_gep_i32(ptr %addr, i32 %ofs) {
+ %arrayidx = getelementptr i32, ptr undef, i32 %ofs
+ ret void
+ }
- define void @test_gep_i64(ptr %addr) {
+ define void @test_gep_i64c(ptr %addr) {
%arrayidx = getelementptr i32, ptr undef, i64 5
ret void
}
+ define void @test_gep_i64(ptr %addr, i64 %ofs) {
+ %arrayidx = getelementptr i32, ptr undef, i64 %ofs
+ ret void
+ }
+...
+---
+name: test_gep_i8c
+legalized: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_gep_i8c
+ ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+ ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; CHECK-NEXT: RET 0
+ %0(p0) = IMPLICIT_DEF
+ %1(s8) = G_CONSTANT i8 20
+ %2(p0) = G_PTR_ADD %0, %1(s8)
+ G_STORE %2, %0 :: (store (p0) into %ir.addr)
+ RET 0
...
---
name: test_gep_i8
@@ -33,17 +71,39 @@ body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i8
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
- ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
- ; CHECK: RET 0
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[DEF1]](s8)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
+ ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
- %1(s8) = G_CONSTANT i8 20
+ %1(s8) = IMPLICIT_DEF
%2(p0) = G_PTR_ADD %0, %1(s8)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
+name: test_gep_i16c
+legalized: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_gep_i16c
+ ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+ ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; CHECK-NEXT: RET 0
+ %0(p0) = IMPLICIT_DEF
+ %1(s16) = G_CONSTANT i16 20
+ %2(p0) = G_PTR_ADD %0, %1(s16)
+ G_STORE %2, %0 :: (store (p0) into %ir.addr)
+ RET 0
+...
+---
name: test_gep_i16
legalized: false
registers:
@@ -54,18 +114,19 @@ body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_gep_i16
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
- ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
- ; CHECK: RET 0
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[DEF1]](s16)
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
+ ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
- %1(s16) = G_CONSTANT i16 20
+ %1(s16) = IMPLICIT_DEF
%2(p0) = G_PTR_ADD %0, %1(s16)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
---
-name: test_gep_i32
+name: test_gep_i32c
legalized: false
registers:
- { id: 0, class: _ }
@@ -73,12 +134,12 @@ registers:
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
- ; CHECK-LABEL: name: test_gep_i32
+ ; CHECK-LABEL: name: test_gep_i32c
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
- ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
- ; CHECK: RET 0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+ ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; CHECK-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s32) = G_CONSTANT i32 20
%2(p0) = G_PTR_ADD %0, %1(s32)
@@ -86,7 +147,7 @@ body: |
RET 0
...
---
-name: test_gep_i64
+name: test_gep_i32
legalized: false
registers:
- { id: 0, class: _ }
@@ -94,15 +155,70 @@ registers:
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
- ; CHECK-LABEL: name: test_gep_i64
+ ; CHECK-LABEL: name: test_gep_i32
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s64)
- ; CHECK: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
- ; CHECK: RET 0
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[DEF1]](s32)
+ ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; CHECK-NEXT: RET 0
+ %0(p0) = IMPLICIT_DEF
+ %1(s32) = IMPLICIT_DEF
+ %2(p0) = G_PTR_ADD %0, %1(s32)
+ G_STORE %2, %0 :: (store (p0) into %ir.addr)
+ RET 0
+...
+---
+name: test_gep_i64c
+legalized: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; X64-LABEL: name: test_gep_i64c
+ ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
+ ; X64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s64)
+ ; X64-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; X64-NEXT: RET 0
+ ; X86-LABEL: name: test_gep_i64c
+ ; X86: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+ ; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+ ; X86-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; X86-NEXT: RET 0
%0(p0) = IMPLICIT_DEF
%1(s64) = G_CONSTANT i64 20
%2(p0) = G_PTR_ADD %0, %1(s64)
G_STORE %2, %0 :: (store (p0) into %ir.addr)
RET 0
...
+---
+name: test_gep_i64
+legalized: false
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.1 (%ir-block.0):
+ ; X64-LABEL: name: test_gep_i64
+ ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[DEF1]](s64)
+ ; X64-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; X64-NEXT: RET 0
+ ; X86-LABEL: name: test_gep_i64
+ ; X86: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X86-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF1]](s64)
+ ; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[TRUNC]](s32)
+ ; X86-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
+ ; X86-NEXT: RET 0
+ %0(p0) = IMPLICIT_DEF
+ %1(s64) = IMPLICIT_DEF
+ %2(p0) = G_PTR_ADD %0, %1(s64)
+ G_STORE %2, %0 :: (store (p0) into %ir.addr)
+ RET 0
+...
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