[llvm] 3a87c15 - [AArch64][NFC] Normalise name of indexed forms of SQRDMLAH/SQRDMLSH

[Ricardo Jesus via llvm-commits]

Author: Ricardo Jesus
Date: 2023-06-06T13:02:36Z
New Revision: 3a87c15026622eae6dc9668b8fbdc8cd11890b07

URL: https://github.com/llvm/llvm-project/commit/3a87c15026622eae6dc9668b8fbdc8cd11890b07
DIFF: https://github.com/llvm/llvm-project/commit/3a87c15026622eae6dc9668b8fbdc8cd11890b07.diff

LOG: [AArch64][NFC] Normalise name of indexed forms of SQRDMLAH/SQRDMLSH

Most indexed vector instructions are suffixed with v<N><TY>_indexed.

SQRDMLAH/SQRDMLSH are the exception, being suffixed with <TY>_indexed
instead, which can complicate matching them slightly.

Differential Revision: https://reviews.llvm.org/D152161

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrFormats.td
    llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 0cd03dbf47718..34be726aeaf59 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -10862,19 +10862,19 @@ multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
     let Inst{21} = idx{0};
   }
 
-  def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
-                                        FPR16Op, FPR16Op, V128_lo,
-                                        VectorIndexH, asm, ".h", "", "", ".h",
-                                        []> {
+  def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
+                                          FPR16Op, FPR16Op, V128_lo,
+                                          VectorIndexH, asm, ".h", "", "", ".h",
+                                          []> {
     bits<3> idx;
     let Inst{11} = idx{2};
     let Inst{21} = idx{1};
     let Inst{20} = idx{0};
   }
 
-  def i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
-                                        FPR32Op, FPR32Op, V128, VectorIndexS,
-                                        asm, ".s", "", "", ".s",
+  def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
+                                          FPR32Op, FPR32Op, V128, VectorIndexS,
+                                          asm, ".s", "", "", ".s",
     [(set (i32 FPR32Op:$dst),
           (i32 (op (i32 FPR32Op:$Rd), (i32 FPR32Op:$Rn),
                    (i32 (vector_extract (v4i32 V128:$Rm),

diff  --git a/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll b/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
index bf938b1a92576..bb13e96532baf 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
@@ -494,7 +494,7 @@ define i32 @test_sqrdmlsh_i32(i32 %acc, i32 %mhs, i32 %rhs) {
 ;-----------------------------------------------------------------------------
 ; RDMA Scalar, by element
 ; i16 tests are performed via tests in above chapter, with IR in ACLE style
-; i32 tests are for i32_indexed in SIMDIndexedSQRDMLxHSDTied
+; i32 tests are for v1i32_indexed in SIMDIndexedSQRDMLxHSDTied
 
 define i16 @test_sqrdmlah_extract_i16(i16 %acc, i16 %x, <4 x i16> %y_vec) {
 ; CHECK-LABEL: test_sqrdmlah_extract_i16: