[PATCH] D150324: [X86] Make constant `mul` -> `shl` + `add`/`sub` work for vector types

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n updated this revision to Diff 526481.
goldstein.w.n added a comment.

On use shift if 1x extra add/sub
Fix some nits


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150324/new/

https://reviews.llvm.org/D150324

Files:
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.h
  llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
  llvm/test/CodeGen/X86/combine-add.ll
  llvm/test/CodeGen/X86/rotate-extract-vector.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
  llvm/test/CodeGen/X86/vector-mul.ll

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