[llvm] 4a92d69 - [X86][MC] Move the code about INC/DEC encoding optimization to X86EncodingOptimization.cpp, NFCI

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2023-05-18T11:11:32+08:00
New Revision: 4a92d69a162449033898dc0c1b1a6966de716a68

URL: https://github.com/llvm/llvm-project/commit/4a92d69a162449033898dc0c1b1a6966de716a68
DIFF: https://github.com/llvm/llvm-project/commit/4a92d69a162449033898dc0c1b1a6966de716a68.diff

LOG: [X86][MC] Move the code about INC/DEC encoding optimization to X86EncodingOptimization.cpp, NFCI

Added: 
    

Modified: 
    llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
    llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h
    llvm/lib/Target/X86/X86MCInstLower.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
index 43a93cbdea29..889430452a4f 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
@@ -261,8 +261,30 @@ bool X86::optimizeMOVSX(MCInst &MI) {
     FROM_TO(MOVSX16rr8, CBW, AX, AL)     // movsbw %al, %ax   --> cbtw
     FROM_TO(MOVSX32rr16, CWDE, EAX, AX)  // movswl %ax, %eax  --> cwtl
     FROM_TO(MOVSX64rr32, CDQE, RAX, EAX) // movslq %eax, %rax --> cltq
+#undef FROM_TO
   }
   MI.clear();
   MI.setOpcode(NewOpc);
   return true;
 }
+
+bool X86::optimizeINCDEC(MCInst &MI, bool In64BitMode) {
+  if (In64BitMode)
+    return false;
+  unsigned NewOpc;
+  // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
+#define FROM_TO(FROM, TO)                                                      \
+  case X86::FROM:                                                              \
+    NewOpc = X86::TO;                                                          \
+    break;
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+    FROM_TO(DEC16r, DEC16r_alt)
+    FROM_TO(DEC32r, DEC32r_alt)
+    FROM_TO(INC16r, INC16r_alt)
+    FROM_TO(INC32r, INC32r_alt)
+  }
+  MI.setOpcode(NewOpc);
+  return true;
+}

diff  --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h
index 1e085e93b355..1177d2c75784 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h
@@ -20,6 +20,7 @@ bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc);
 bool optimizeShiftRotateWithImmediateOne(MCInst &MI);
 bool optimizeVPCMPWithImmediateOneOrSix(MCInst &MI);
 bool optimizeMOVSX(MCInst &MI);
+bool optimizeINCDEC(MCInst &MI, bool In64BitMode);
 } // namespace X86
 } // namespace llvm
 #endif

diff  --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index c68a9d2623c2..ff3b41bd24c4 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -486,6 +486,10 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   if (X86::optimizeMOVSX(OutMI))
     return;
 
+  bool In64BitMode = AsmPrinter.getSubtarget().is64Bit();
+  if (X86::optimizeINCDEC(OutMI, In64BitMode))
+    return;
+
   // Handle a few special cases to eliminate operand modifiers.
   switch (OutMI.getOpcode()) {
   case X86::LEA64_32r:
@@ -545,7 +549,7 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   case X86::CATCHRET: {
     // Replace CATCHRET with the appropriate RET.
     const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
-    unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
+    unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX;
     OutMI = MCInst();
     OutMI.setOpcode(getRetOpcode(Subtarget));
     OutMI.addOperand(MCOperand::createReg(ReturnReg));
@@ -577,24 +581,6 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
     OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
     break;
 
-  case X86::DEC16r:
-  case X86::DEC32r:
-  case X86::INC16r:
-  case X86::INC32r:
-    // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
-    if (!AsmPrinter.getSubtarget().is64Bit()) {
-      unsigned Opcode;
-      switch (OutMI.getOpcode()) {
-      default: llvm_unreachable("Invalid opcode");
-      case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
-      case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
-      case X86::INC16r: Opcode = X86::INC16r_alt; break;
-      case X86::INC32r: Opcode = X86::INC32r_alt; break;
-      }
-      OutMI.setOpcode(Opcode);
-    }
-    break;
-
   // We don't currently select the correct instruction form for instructions
   // which have a short %eax, etc. form. Handle this by custom lowering, for
   // now.
@@ -703,7 +689,7 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   }
   case X86::MASKMOVDQU:
   case X86::VMASKMOVDQU:
-    if (AsmPrinter.getSubtarget().is64Bit())
+    if (In64BitMode)
       OutMI.setFlags(X86::IP_HAS_AD_SIZE);
     break;