[PATCH] D150798: [RISCV] Implement storeOfVectorConstantIsCheap hook to prevent store merging at VL=2

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:538
+    // in instructions even after we add a vector constant load.
+    return NumElem >= 4;
+  }
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I notice X86 uses > 2 and your patch description talks about VL=2 and mentions being similar to X86, but you've used 4 here. Is 3 supported by store merging?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D150798/new/

https://reviews.llvm.org/D150798