[PATCH] D150671: RISCV/InstrInfo: model register pressure for MICombiner

[Ramkumar Ramachandra via Phabricator via llvm-commits]

artagnon created this revision.
artagnon added reviewers: craig.topper, asb, reames.
Herald added subscribers: luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
artagnon requested review of this revision.
Herald added subscribers: llvm-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

We have a set of general purpose registers defined for RISC-V (32),
after which we can model the register pressure, inspired by the way it's
modeled in PPC. The motivation for this change is to get MachineCombiner
to not increase register pressure when re-ordering instructions.
Unfortunately, it's very hard to tell if a particular MICombiner
transform will increase register pressure without actually doing the
transform and re-computing register pressure. The workaround that LLVM
has for this is to predicate the transform on
shouldReduceRegisterPressure(), which should ideally tell us when we're
running out of registers. Hence, implement
shouldReduceRegisterPressure() for RISC-V, using the number of general
purpose registers as the limit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150671

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D150671.522614.patch
Type: text/x-patch
Size: 5331 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230516/d2b7bbdd/attachment.bin>