[PATCH] D150177: [RISCV] Enable signed truncation check transforms for i8

[Yingwei Zheng via Phabricator via llvm-commits]

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This patch enables signed truncation check transforms for i8 on rv32 when XVT is i64 and Zbb is enabled.

It is a small improvement of D149977 <https://reviews.llvm.org/D149977>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150177

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll
  llvm/test/CodeGen/RISCV/signed-truncation-check.ll

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