[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:278
+    assert(MBBI->getOperand(2).getOffset() == 0);
+    MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
+    BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
----------------
craig.topper wrote:
> craig.topper wrote:
> > This doesn't work. The load/store is paired with an LUI. The offset in the LUI needs to match. This just moved the overflow to the linker.
> I guess if the global is 8 byte aligned, the +4 won't cause any wrap.
The current test affected by this code is fld_fsd_global in double-mem.ll. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149743/new/

https://reviews.llvm.org/D149743