[PATCH] D148185: Add more efficient bitwise vector reductions on AArch64

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Can you rebase over D148672 <https://reviews.llvm.org/D148672>, now that that is in?



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Comment at: llvm/test/CodeGen/AArch64/reduce-and.ll:259
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, w1
-; CHECK-NEXT:    and w8, w8, w2
-; CHECK-NEXT:    and w0, w8, #0xff
+; CHECK-NEXT:    movi d0, #0xff00ff00ff00ff
+; CHECK-NEXT:    mov v0.h[0], w0
----------------
I'm surprised this passes vectors in gpr registers. It would be quite different for values vector regs.


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  https://reviews.llvm.org/D148185/new/

https://reviews.llvm.org/D148185