[PATCH] D149486: [RISCV] Strengthen atomic ordering for sequentially consistent Loads

[Paul Kirth via Phabricator via llvm-commits]

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This is a similar change to one proposed for GCC:
https://inbox.sourceware.org/gcc-patches/20230414170942.1695672-1-patrick@rivosinc.com/

The changes in this patch are based on the proposal by Hans Boehm to more
closely match the intended semantics and avoid an ABI break in the future.
Further details can be found in the psABI proposal:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/378.

This patch implements a mapping that is stronger than the one outlined in table
A.6 of the RISC-V unprivileged spec to be future compatible with table A.7 of
the same document. The related discussion can be found at
https://lists.riscv.org/g/tech-unprivileged/topic/risc_v_memory_model_topics/92916241

The major change to RISC-V code generation is that we will now emit a trailing
fence for sequentially consistent stores.

The new code sequence should have the following form:

  fence rw,w; s{b|h|w|d}; fence rw,rw;

Other changes and optimizations like using amoswap will be handled separately.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149486

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/atomic-load-store.ll
  llvm/test/CodeGen/RISCV/forced-atomics.ll

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