[llvm] 7f0a881 - [AMDGPU] Track liveins for max-ilp-sched-strategy

[Jeffrey Byrnes via llvm-commits]

Author: Jeffrey Byrnes
Date: 2023-04-27T16:45:45-07:00
New Revision: 7f0a881e6c3513914fd51b9ad3b3ac0b556af807

URL: https://github.com/llvm/llvm-project/commit/7f0a881e6c3513914fd51b9ad3b3ac0b556af807
DIFF: https://github.com/llvm/llvm-project/commit/7f0a881e6c3513914fd51b9ad3b3ac0b556af807.diff

LOG: [AMDGPU] Track liveins for max-ilp-sched-strategy

Even if optimizing for ILP, it is still useful to track RP to avoid spilling. Given that, we need to maintin consistent liveness state with the RP tracker. This patch makes RP tracking consistent by updating for liveins.

Otherwise, we should completely eliminate RP tracking for this scheduler (checkScheduling, initCandidate).

Differential Revision: https://reviews.llvm.org/D149358

Added: 
    llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir

Modified: 
    llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 7f7d6e56874c..32fd64f1140d 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -872,7 +872,8 @@ void GCNSchedStage::setupNewBlock() {
   DAG.startBlock(CurrentMBB);
   // Get real RP for the region if it hasn't be calculated before. After the
   // initial schedule stage real RP will be collected after scheduling.
-  if (StageID == GCNSchedStageID::OccInitialSchedule)
+  if (StageID == GCNSchedStageID::OccInitialSchedule ||
+      StageID == GCNSchedStageID::ILPInitialSchedule)
     DAG.computeBlockPressure(RegionIdx, CurrentMBB);
 }
 

diff  --git a/llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir b/llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
new file mode 100644
index 000000000000..4b6e204ecf95
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/schedule-ilp-liveness-tracking.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -amdgpu-enable-max-ilp-scheduling-strategy -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+---
+name:            max-ilp-liveness-tracking
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: max-ilp-liveness-tracking
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %src0:vgpr_32 = V_MOV_B32_e64 0, implicit $exec
+  ; CHECK-NEXT:   %src1:vgpr_32 = V_MOV_B32_e64 1, implicit $exec
+  ; CHECK-NEXT:   %live0:vgpr_32 = V_ADD_U32_e32 %src0, %src1, implicit $exec
+  ; CHECK-NEXT:   %live1:vgpr_32 = V_ADD_U32_e32 %live0, %src1, implicit $exec
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   %out0:vgpr_32 = V_ADD_U32_e32 %live0, %live1, implicit $exec
+  ; CHECK-NEXT:   dead %out1:vgpr_32 = V_ADD_U32_e32 %out0, %live1, implicit $exec
+  ; CHECK-NEXT:   S_ENDPGM 0
+  bb.0:
+    successors: %bb.1
+    %src0:vgpr_32 = V_MOV_B32_e64 0, implicit $exec
+    %src1:vgpr_32 = V_MOV_B32_e64 1, implicit $exec
+    %live0:vgpr_32 = V_ADD_U32_e32 %src0:vgpr_32, %src1:vgpr_32, implicit $exec
+    %live1:vgpr_32 = V_ADD_U32_e32 %live0:vgpr_32, %src1:vgpr_32, implicit $exec
+
+  bb.1:
+    %out0:vgpr_32 = V_ADD_U32_e32 %live0:vgpr_32, %live1:vgpr_32, implicit $exec
+    %out1:vgpr_32 = V_ADD_U32_e32 %out0:vgpr_32, %live1:vgpr_32, implicit $exec
+    S_ENDPGM 0
+
+...