[PATCH] D149080: [AMDGPU] Fix negative offset values interpretation in getMemOperandsWithOffset for DS

[Janek van Oirschot via Phabricator via llvm-commits]

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The offset values may result in an erroneous scheduling of a load before write for a memory location if the offset values are represented as negative values in MIR, despite actually being unsigned values. This representation in MIR happens as SelectionDAG::getConstant could go through APInt to represent the encoding which assumes the MSB of the encoding as a sign-bit, regardless of whether it is supposed to be a signed value. The 8-bit negative (interpreted) value gets cast to an unsigned 32 bit value in getMemOperandsWithOffset used for comparisons in areMemAccessesTriviallyDisjoint eventually leading to an erroneous schedule in the machine scheduler.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149080

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir

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