[PATCH] D141473: [PowerPC] Simplify fp-to-int store optimization

Qiu Chaofan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 13 19:58:04 PDT 2023


qiucf added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14878
-                    dl, ResVT == MVT::f128 ? MVT::f128 : MVT::f64, Val);
-  DCI.AddToWorklist(Val.getNode());
 
----------------
qiucf wrote:
> shchenz wrote:
> > We may need to following this logic and consider about adding the users back to the work list.
> Is that necessary? DAG combiner will add the users into worklist.
The root node to be returned is the `ST_VSR_SCAL_INT`, then `FCTIDZ`, then `FP_EXTEND` (if f32). The `FP_EXTEND` from f32 to f64 will disappear after ISel. The others are PPC-specific nodes so adding them into worklist manually will not help.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141473/new/

https://reviews.llvm.org/D141473



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