[PATCH] D147934: [RISCV] Support LLVM IR intrinsics for XSfvcp extension.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td:467
+    if !ge(vti.SEW, 16) then {
+    defm : VPatVC_XV<"fv", "F" # vti.SEW # "V", vti,
+                     GetFTypeInfo<vti.SEW>.Scalar,
----------------
Indent these since the `if` created a new scope


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td:482
+    if !ge(vti.SEW, 16) then {
+    defm : VPatVC_XVV<"fvw", "F" # vti.SEW # "VW", wti, vti,
+                      GetFTypeInfo<vti.SEW>.Scalar,
----------------
Indent


================
Comment at: llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll:239
+
+declare void @llvm.riscv.sf.vc.x.se.e32m8.iXLen.i32.iXLen(iXLen, iXLen, iXLen, i32, iXLen)
+
----------------
Why is there no test for the e64 version of this intrinsic?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147934/new/

https://reviews.llvm.org/D147934