[PATCH] D146949: [Xtensa] Lower SHIFT PARTS and shift operations.

[Maciej Czekaj via Phabricator via llvm-commits]

maciejcz added a comment.
Herald added a subscriber: sstefan1.

The code conforms to ISA. One doubt about the opcode used for comparing shift amount with 32.



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Comment at: llvm/lib/Target/Xtensa/XtensaISelLowering.cpp:857
+  SDValue ShiftLeftLo = DAG.getNode(XtensaISD::SHL, DL, VT, Lo, SetShiftLeft1);
+  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
+                             DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
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This comment applies to other SELECT nodes as well.
Why the condtion is `Shamt & 32` as opposed to `Shamt < 32`? or at least `Shamt & 31` ?
Other targets (see RISC-V) use `Shamt < 32`.


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https://reviews.llvm.org/D146949