[PATCH] D147119: [RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.

Kito Cheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 5 18:36:04 PDT 2023


kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147119/new/

https://reviews.llvm.org/D147119



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