[llvm] b4089cf - [NFC][LoopVectorize] Simplify preferPredicateOverEpilogue interface
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 4 07:01:40 PDT 2023
Author: David Sherwood
Date: 2023-04-04T14:00:49Z
New Revision: b4089cfa2fc3449a2e124804d34ba8fb591e55c5
URL: https://github.com/llvm/llvm-project/commit/b4089cfa2fc3449a2e124804d34ba8fb591e55c5
DIFF: https://github.com/llvm/llvm-project/commit/b4089cfa2fc3449a2e124804d34ba8fb591e55c5.diff
LOG: [NFC][LoopVectorize] Simplify preferPredicateOverEpilogue interface
Given just how many arguments we pass to
preferPredicateOverEpilogue and considering this list may
grow over time I've decided to pass in a pointer to a new
TailFoldingInfo structure instead, similar to what we do
with IntrinsicCostAttributes, etc. In addition, many of the
arguments we pass in are actually available in the
LoopVectorizationLegality class so I've managed to
reduce the set of pointers that we need to pass in the
TailFoldingInfo struct.
Differential Revision: https://reviews.llvm.org/D146127
Added:
Modified:
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/include/llvm/CodeGen/BasicTTIImpl.h
llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index c3e50addc7c6b..7ffeffee18162 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -192,6 +192,15 @@ enum class TailFoldingStyle {
DataAndControlFlowWithoutRuntimeCheck
};
+struct TailFoldingInfo {
+ TargetLibraryInfo *TLI;
+ LoopVectorizationLegality *LVL;
+ InterleavedAccessInfo *IAI;
+ TailFoldingInfo(TargetLibraryInfo *TLI, LoopVectorizationLegality *LVL,
+ InterleavedAccessInfo *IAI)
+ : TLI(TLI), LVL(LVL), IAI(IAI) {}
+};
+
class TargetTransformInfo;
typedef TargetTransformInfo TTI;
@@ -583,11 +592,7 @@ class TargetTransformInfo {
/// Query the target whether it would be prefered to create a predicated
/// vector loop, which can avoid the need to emit a scalar epilogue loop.
- bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
- AssumptionCache &AC, TargetLibraryInfo *TLI,
- DominatorTree *DT,
- LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI) const;
+ bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const;
/// Query the target what the preferred style of tail folding is.
/// \param IVUpdateMayOverflow Tells whether it is known if the IV update
@@ -1703,11 +1708,7 @@ class TargetTransformInfo::Concept {
AssumptionCache &AC,
TargetLibraryInfo *LibInfo,
HardwareLoopInfo &HWLoopInfo) = 0;
- virtual bool
- preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
- AssumptionCache &AC, TargetLibraryInfo *TLI,
- DominatorTree *DT, LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI) = 0;
+ virtual bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) = 0;
virtual TailFoldingStyle
getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) = 0;
virtual std::optional<Instruction *> instCombineIntrinsic(
@@ -2110,12 +2111,8 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
HardwareLoopInfo &HWLoopInfo) override {
return Impl.isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
}
- bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
- AssumptionCache &AC, TargetLibraryInfo *TLI,
- DominatorTree *DT,
- LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI) override {
- return Impl.preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LVL, IAI);
+ bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) override {
+ return Impl.preferPredicateOverEpilogue(TFI);
}
TailFoldingStyle
getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) override {
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index dd2de49dcd12d..fbd5202097014 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -163,13 +163,7 @@ class TargetTransformInfoImplBase {
return false;
}
- bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
- AssumptionCache &AC, TargetLibraryInfo *TLI,
- DominatorTree *DT,
- LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI) const {
- return false;
- }
+ bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const { return false; }
TailFoldingStyle
getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const {
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 5517ad7ee156e..c6c741c831e68 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -622,12 +622,8 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
return BaseT::isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
}
- bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
- AssumptionCache &AC, TargetLibraryInfo *TLI,
- DominatorTree *DT,
- LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI) {
- return BaseT::preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LVL, IAI);
+ bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) {
+ return BaseT::preferPredicateOverEpilogue(TFI);
}
TailFoldingStyle
diff --git a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
index 6c423274986dd..45d786e71f9e9 100644
--- a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
+++ b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
@@ -392,6 +392,16 @@ class LoopVectorizationLegality {
return &PSE;
}
+ Loop *getLoop() const { return TheLoop; }
+
+ LoopInfo *getLoopInfo() const { return LI; }
+
+ AssumptionCache *getAssumptionCache() const { return AC; }
+
+ ScalarEvolution *getScalarEvolution() const { return PSE.getSE(); }
+
+ DominatorTree *getDominatorTree() const { return DT; }
+
private:
/// Return true if the pre-header, exiting and latch blocks of \p Lp and all
/// its nested loops are considered legal for vectorization. These legal
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index cdeffcbd8c5c1..a29ccf0653b65 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -322,10 +322,8 @@ bool TargetTransformInfo::isHardwareLoopProfitable(
}
bool TargetTransformInfo::preferPredicateOverEpilogue(
- Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
- TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI) const {
- return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LVL, IAI);
+ TailFoldingInfo *TFI) const {
+ return TTIImpl->preferPredicateOverEpilogue(TFI);
}
TailFoldingStyle TargetTransformInfo::getPreferredTailFoldingStyle(
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index f145ae8b269a0..df8eff2812cf2 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -3410,29 +3410,27 @@ static bool containsDecreasingPointers(Loop *TheLoop,
return false;
}
-bool AArch64TTIImpl::preferPredicateOverEpilogue(
- Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
- TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI) {
+bool AArch64TTIImpl::preferPredicateOverEpilogue(TailFoldingInfo *TFI) {
if (!ST->hasSVE() || TailFoldingKindLoc == TailFoldingKind::TFDisabled)
return false;
// We don't currently support vectorisation with interleaving for SVE - with
// such loops we're better off not using tail-folding. This gives us a chance
// to fall back on fixed-width vectorisation using NEON's ld2/st2/etc.
- if (IAI->hasGroups())
+ if (TFI->IAI->hasGroups())
return false;
TailFoldingKind Required; // Defaults to 0.
- if (LVL->getReductionVars().size())
+ if (TFI->LVL->getReductionVars().size())
Required.add(TailFoldingKind::TFReductions);
- if (LVL->getFixedOrderRecurrences().size())
+ if (TFI->LVL->getFixedOrderRecurrences().size())
Required.add(TailFoldingKind::TFRecurrences);
// We call this to discover whether any load/store pointers in the loop have
// negative strides. This will require extra work to reverse the loop
// predicate, which may be expensive.
- if (containsDecreasingPointers(L, LVL->getPredicatedScalarEvolution()))
+ if (containsDecreasingPointers(TFI->LVL->getLoop(),
+ TFI->LVL->getPredicatedScalarEvolution()))
Required.add(TailFoldingKind::TFReverse);
if (!Required)
Required.add(TailFoldingKind::TFSimple);
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index df69c37ef83c9..de8b2c60a7974 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -358,11 +358,7 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
return TailFoldingStyle::DataWithoutLaneMask;
}
- bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
- AssumptionCache &AC, TargetLibraryInfo *TLI,
- DominatorTree *DT,
- LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI);
+ bool preferPredicateOverEpilogue(TailFoldingInfo *TFI);
bool supportsScalableVectors() const { return ST->hasSVE(); }
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index 4be20c35d0940..6301521da6afb 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -2238,10 +2238,7 @@ static bool canTailPredicateLoop(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
return true;
}
-bool ARMTTIImpl::preferPredicateOverEpilogue(
- Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
- TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI) {
+bool ARMTTIImpl::preferPredicateOverEpilogue(TailFoldingInfo *TFI) {
if (!EnableTailPredication) {
LLVM_DEBUG(dbgs() << "Tail-predication not enabled.\n");
return false;
@@ -2253,6 +2250,9 @@ bool ARMTTIImpl::preferPredicateOverEpilogue(
if (!ST->hasMVEIntegerOps())
return false;
+ LoopVectorizationLegality *LVL = TFI->LVL;
+ Loop *L = LVL->getLoop();
+
// For now, restrict this to single block loops.
if (L->getNumBlocks() > 1) {
LLVM_DEBUG(dbgs() << "preferPredicateOverEpilogue: not a single block "
@@ -2262,6 +2262,7 @@ bool ARMTTIImpl::preferPredicateOverEpilogue(
assert(L->isInnermost() && "preferPredicateOverEpilogue: inner-loop expected");
+ LoopInfo *LI = LVL->getLoopInfo();
HardwareLoopInfo HWLoopInfo(L);
if (!HWLoopInfo.canAnalyze(*LI)) {
LLVM_DEBUG(dbgs() << "preferPredicateOverEpilogue: hardware-loop is not "
@@ -2269,21 +2270,25 @@ bool ARMTTIImpl::preferPredicateOverEpilogue(
return false;
}
+ AssumptionCache *AC = LVL->getAssumptionCache();
+ ScalarEvolution *SE = LVL->getScalarEvolution();
+
// This checks if we have the low-overhead branch architecture
// extension, and if we will create a hardware-loop:
- if (!isHardwareLoopProfitable(L, SE, AC, TLI, HWLoopInfo)) {
+ if (!isHardwareLoopProfitable(L, *SE, *AC, TFI->TLI, HWLoopInfo)) {
LLVM_DEBUG(dbgs() << "preferPredicateOverEpilogue: hardware-loop is not "
"profitable.\n");
return false;
}
- if (!HWLoopInfo.isHardwareLoopCandidate(SE, *LI, *DT)) {
+ DominatorTree *DT = LVL->getDominatorTree();
+ if (!HWLoopInfo.isHardwareLoopCandidate(*SE, *LI, *DT)) {
LLVM_DEBUG(dbgs() << "preferPredicateOverEpilogue: hardware-loop is not "
"a candidate.\n");
return false;
}
- return canTailPredicateLoop(L, LI, SE, DL, LVL->getLAI());
+ return canTailPredicateLoop(L, LI, *SE, DL, LVL->getLAI());
}
TailFoldingStyle
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index 40c14be6f41bc..1f04b412d894f 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -303,11 +303,7 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
AssumptionCache &AC,
TargetLibraryInfo *LibInfo,
HardwareLoopInfo &HWLoopInfo);
- bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
- AssumptionCache &AC, TargetLibraryInfo *TLI,
- DominatorTree *DT,
- LoopVectorizationLegality *LVL,
- InterleavedAccessInfo *IAI);
+ bool preferPredicateOverEpilogue(TailFoldingInfo *TFI);
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
TTI::UnrollingPreferences &UP,
OptimizationRemarkEmitter *ORE);
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 0b369f9c70e56..ad299ea8a2482 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -9723,7 +9723,6 @@ void VPWidenMemoryInstructionRecipe::execute(VPTransformState &State) {
static ScalarEpilogueLowering getScalarEpilogueLowering(
Function *F, Loop *L, LoopVectorizeHints &Hints, ProfileSummaryInfo *PSI,
BlockFrequencyInfo *BFI, TargetTransformInfo *TTI, TargetLibraryInfo *TLI,
- AssumptionCache *AC, LoopInfo *LI, ScalarEvolution *SE, DominatorTree *DT,
LoopVectorizationLegality &LVL, InterleavedAccessInfo *IAI) {
// 1) OptSize takes precedence over all other options, i.e. if this is set,
// don't look at hints or options, and don't request a scalar epilogue.
@@ -9759,7 +9758,8 @@ static ScalarEpilogueLowering getScalarEpilogueLowering(
};
// 4) if the TTI hook indicates this is profitable, request predication.
- if (TTI->preferPredicateOverEpilogue(L, LI, *SE, *AC, TLI, DT, &LVL, IAI))
+ TailFoldingInfo TFI(TLI, &LVL, IAI);
+ if (TTI->preferPredicateOverEpilogue(&TFI))
return CM_ScalarEpilogueNotNeededUsePredicate;
return CM_ScalarEpilogueAllowed;
@@ -9852,8 +9852,8 @@ static bool processLoopInVPlanNativePath(
Function *F = L->getHeader()->getParent();
InterleavedAccessInfo IAI(PSE, L, DT, LI, LVL->getLAI());
- ScalarEpilogueLowering SEL = getScalarEpilogueLowering(
- F, L, Hints, PSI, BFI, TTI, TLI, AC, LI, PSE.getSE(), DT, *LVL, &IAI);
+ ScalarEpilogueLowering SEL =
+ getScalarEpilogueLowering(F, L, Hints, PSI, BFI, TTI, TLI, *LVL, &IAI);
LoopVectorizationCostModel CM(SEL, L, PSE, LI, LVL, *TTI, TLI, DB, AC, ORE, F,
&Hints, IAI);
@@ -10121,8 +10121,8 @@ bool LoopVectorizePass::processLoop(Loop *L) {
// Check the function attributes and profiles to find out if this function
// should be optimized for size.
- ScalarEpilogueLowering SEL = getScalarEpilogueLowering(
- F, L, Hints, PSI, BFI, TTI, TLI, AC, LI, PSE.getSE(), DT, LVL, &IAI);
+ ScalarEpilogueLowering SEL =
+ getScalarEpilogueLowering(F, L, Hints, PSI, BFI, TTI, TLI, LVL, &IAI);
// Check the loop for a trip count threshold: vectorize loops with a tiny trip
// count by optimizing for size, to minimize overheads.
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