[PATCH] D147212: [ARM] Handle generating SEH unwind info for t2STR_PRE/t2LDR_POST

[Martin Storsjö via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc5383536cb68: [ARM] Handle generating SEH unwind info for t2STR_PRE/t2LDR_POST (authored by mstorsjo).

Changed prior to commit:
  https://reviews.llvm.org/D147212?vs=509595&id=509925#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147212/new/

https://reviews.llvm.org/D147212

Files:
  llvm/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll


Index: llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
===================================================================
--- llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
+++ llvm/test/CodeGen/ARM/Windows/wineh-opcodes.ll
@@ -311,3 +311,31 @@
 }
 
 declare arm_aapcs_vfpcc void @useptr(ptr noundef)
+
+; CHECK-LABEL: func_fp:
+; CHECK-NEXT: .seh_proc func_fp
+; CHECK-NEXT: @ %bb.0:                                @ %entry
+; CHECK-NEXT:         str     r11, [sp, #-4]!
+; CHECK-NEXT:         .seh_save_regs_w        {r11}
+; CHECK-NEXT:         mov     r11, sp
+; CHECK-NEXT:         .seh_save_sp    r11
+; CHECK-NEXT:         .seh_endprologue
+
+; CHECK-NEXT:         mov     r0, r11
+
+; CHECK-NEXT:         .seh_startepilogue
+; CHECK-NEXT:         ldr     r11, [sp], #4
+; CHECK-NEXT:         .seh_save_regs_w        {r11}
+; CHECK-NEXT:         bx      lr
+; CHECK-NEXT:         .seh_nop
+; CHECK-NEXT:         .seh_endepilogue
+; CHECK-NEXT:         .seh_endproc
+
+define arm_aapcs_vfpcc i32 @func_fp() {
+entry:
+  %0 = tail call ptr @llvm.frameaddress.p0(i32 0)
+  %1 = ptrtoint ptr %0 to i32
+  ret i32 %1
+}
+
+declare ptr @llvm.frameaddress.p0(i32 immarg)
Index: llvm/lib/Target/ARM/ARMFrameLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -357,6 +357,34 @@
               .setMIFlags(Flags);
     break;
 
+  case ARM::t2STR_PRE:
+    if (MBBI->getOperand(0).getReg() == ARM::SP &&
+        MBBI->getOperand(2).getReg() == ARM::SP &&
+        MBBI->getOperand(3).getImm() == -4) {
+      unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
+      MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
+                .addImm(1 << Reg)
+                .addImm(/*Wide=*/1)
+                .setMIFlags(Flags);
+    } else {
+      report_fatal_error("No matching SEH Opcode for t2STR_PRE");
+    }
+    break;
+
+  case ARM::t2LDR_POST:
+    if (MBBI->getOperand(1).getReg() == ARM::SP &&
+        MBBI->getOperand(2).getReg() == ARM::SP &&
+        MBBI->getOperand(3).getImm() == 4) {
+      unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
+      MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs))
+                .addImm(1 << Reg)
+                .addImm(/*Wide=*/1)
+                .setMIFlags(Flags);
+    } else {
+      report_fatal_error("No matching SEH Opcode for t2LDR_POST");
+    }
+    break;
+
   case ARM::t2LDMIA_RET:
   case ARM::t2LDMIA_UPD:
   case ARM::t2STMDB_UPD: {


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