[PATCH] D146554: [BOLT][RISCV] Implement R_RISCV_ADD32/SUB32

[Job Noorman via Phabricator via llvm-commits]

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Thispatch implements the R_RISCV_ADD32 and R_RISCV_SUB32 relocations for
RISC-V.

Note that this is meant as a showcase for D146546 <https://reviews.llvm.org/D146546>. This patch still
needs tests before it can land; I will add them later.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146554

Files:
  bolt/lib/Core/Relocation.cpp
  bolt/lib/Rewrite/RewriteInstance.cpp


Index: bolt/lib/Rewrite/RewriteInstance.cpp
===================================================================
--- bolt/lib/Rewrite/RewriteInstance.cpp
+++ bolt/lib/Rewrite/RewriteInstance.cpp
@@ -2921,11 +2921,9 @@
   if (IsFromCode) {
     ContainingBF->addRelocation(Rel.getOffset(), ReferencedSymbol, RType,
                                 Addend, ExtractedValue);
-  } else if (IsToCode || ForceRelocation) {
+  } else {
     BC->addRelocation(Rel.getOffset(), ReferencedSymbol, RType, Addend,
                       ExtractedValue);
-  } else {
-    LLVM_DEBUG(dbgs() << "BOLT-DEBUG: ignoring relocation from data to data\n");
   }
 }
 
Index: bolt/lib/Core/Relocation.cpp
===================================================================
--- bolt/lib/Core/Relocation.cpp
+++ bolt/lib/Core/Relocation.cpp
@@ -103,6 +103,8 @@
   case ELF::R_RISCV_PCREL_LO12_I:
   case ELF::R_RISCV_RVC_JUMP:
   case ELF::R_RISCV_RVC_BRANCH:
+  case ELF::R_RISCV_ADD32:
+  case ELF::R_RISCV_SUB32:
     return true;
   }
 }
@@ -196,6 +198,8 @@
   case ELF::R_RISCV_32_PCREL:
   case ELF::R_RISCV_CALL:
   case ELF::R_RISCV_CALL_PLT:
+  case ELF::R_RISCV_ADD32:
+  case ELF::R_RISCV_SUB32:
     return 4;
   case ELF::R_RISCV_GOT_HI20:
     // See extractValueRISCV for why this is necessary.
@@ -508,6 +512,9 @@
     return SignExtend64<11>(Contents >> 2);
   case ELF::R_RISCV_RVC_BRANCH:
     return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0));
+  case ELF::R_RISCV_ADD32:
+  case ELF::R_RISCV_SUB32:
+    return Contents;
   }
 }
 
@@ -667,6 +674,9 @@
   switch (Type) {
   default:
     llvm_unreachable("Unknown relocation type");
+  case ELF::R_RISCV_ADD32:
+  case ELF::R_RISCV_SUB32:
+    return false;
   case ELF::R_RISCV_JAL:
   case ELF::R_RISCV_CALL:
   case ELF::R_RISCV_CALL_PLT:
@@ -858,7 +868,16 @@
 }
 
 MCBinaryExpr::Opcode Relocation::getComposeOpcodeFor(uint64_t Type) {
-  llvm_unreachable("not implemented");
+  assert(Arch == Triple::riscv64 && "only implemented for RISC-V");
+
+  switch (Type) {
+  default:
+    llvm_unreachable("not implemented");
+  case ELF::R_RISCV_ADD32:
+    return MCBinaryExpr::Add;
+  case ELF::R_RISCV_SUB32:
+    return MCBinaryExpr::Sub;
+  }
 }
 
 #define ELF_RELOC(name, value) #name,


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