[llvm] 34f1da3 - [RISCV] Make Zfh PseudoQuietFCMP definitions predicated on HasStdExtZfh

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2023-03-20T17:05:48Z
New Revision: 34f1da3468ab70b182072ddbe9e2784b3bde9923

URL: https://github.com/llvm/llvm-project/commit/34f1da3468ab70b182072ddbe9e2784b3bde9923
DIFF: https://github.com/llvm/llvm-project/commit/34f1da3468ab70b182072ddbe9e2784b3bde9923.diff

LOG: [RISCV] Make Zfh PseudoQuietFCMP definitions predicated on HasStdExtZfh

These are currently in a `Predicates = [HasStdExtZfhOrZfhmin]` block,
but Zfhmin has no fcmp instructions so the definition makes no sense for
Zfhmin.

Differential Revision: https://reviews.llvm.org/D146435

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 43e8fa1dfe0e3..3ff445e1397d8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -206,15 +206,16 @@ def : InstAlias<"fgt.h $rd, $rs, $rt",
                 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 def : InstAlias<"fge.h $rd, $rs, $rt",
                 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
-} // Predicates = [HasStdExtZfh]
 
-let Predicates = [HasStdExtZfhOrZfhmin] in {
-def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
-def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 let usesCustomInserter = 1 in {
 def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>;
 def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>;
 }
+} // Predicates = [HasStdExtZfh]
+
+let Predicates = [HasStdExtZfhOrZfhmin] in {
+def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
+def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 } // Predicates = [HasStdExtZfhOrZfhmin]
 
 let Predicates = [HasStdExtZhinx] in {