[PATCH] D143335: [AMDGPU] Use instruction order in machine function to process workList of moveToVALU

[krishna chaitanya sankisa via Phabricator via llvm-commits]

skc7 added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:69
+    return {};
+  ReversePostOrderTraversal<const MachineBasicBlock *> RPOT(&*MF->begin());
+  std::vector<const MachineBasicBlock *> RPOList;
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arsenm wrote:
> It doesn't make sense to me to construct RPO to create a list like this. The whole iteration would just work in RPO
AFAIU, MBB order is created using RPOT list. New MBB might get created by legalizeOperands method once an instruction is processed in the worklist and the MBB order might change. So this list needs to be re-generated.
This list will be used by Cmp::Operator() to compare instructions from two different basic blocks.  


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:75-77
+// Compare machine instructions based on their order
+// in the machine function. Returns true if first instruction
+// occurs before second instruction in the machine function.
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arsenm wrote:
> This should be implied by the iteration order, shouldn't need to sort
New MachineInstructions might get added to worklist after it gets processed by legalizeOperands. So we need to maintain a sorted order of worklist. So, we need a Cmp::operator() for sort.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D143335/new/

https://reviews.llvm.org/D143335