[PATCH] D136862: [AArch64][SME2] Add CodeGen support for target("aarch64.svcount").

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

A couple of minor issues but otherwise looks good.



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Comment at: llvm/include/llvm/CodeGen/ValueTypes.h:125
     bool isZeroSized() const {
-      return !isScalableVector() && getSizeInBits() == 0;
+      return getSizeInBits().getKnownMinValue() == 0;
     }
----------------
Can you use `isZero()` here?


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Comment at: llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll:168-172
+;define target("aarch64.svcount") @test_sel_cc(target("aarch64.svcount") %x, target("aarch64.svcount") %y, i32 %k) {
+;  %cmp = icmp sgt i32 %k, 42
+;  %x.y = select i1 %cmp, target("aarch64.svcount") %x, target("aarch64.svcount") %y
+;  ret target("aarch64.svcount") %x.y
+;}
----------------
Commented out test.


Repository:
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  https://reviews.llvm.org/D136862/new/

https://reviews.llvm.org/D136862