[llvm] c86f8d4 - [PowerPC] Don't crash when disassembling invalid immediate

[Nemanja Ivanovic via llvm-commits]

Author: Nemanja Ivanovic
Date: 2023-02-02T12:39:49-06:00
New Revision: c86f8d4276aee8956711829e49c9969cd0223590

URL: https://github.com/llvm/llvm-project/commit/c86f8d4276aee8956711829e49c9969cd0223590
DIFF: https://github.com/llvm/llvm-project/commit/c86f8d4276aee8956711829e49c9969cd0223590.diff

LOG: [PowerPC] Don't crash when disassembling invalid immediate

There is an assert in the disassembler functions to ensure
that the immediate is the appropriate width. However,
sometimes what is being disassembled is not instructions
but data that happens to have the bit pattern of an existing
instruction but invalid operands. It is valid for such
things to exist in the text section so we don't want
to crash when disassembling such a thing.

This patch removes the asserts and produces a disassembler
failure for such cases.

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
    llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 1629f1b2810f6..57047271dac80 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -239,7 +239,8 @@ template <unsigned N>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address,
                                       const MCDisassembler *Decoder) {
-  assert(isUInt<N>(Imm) && "Invalid immediate");
+  if (!isUInt<N>(Imm))
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
@@ -248,7 +249,8 @@ template <unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address,
                                       const MCDisassembler *Decoder) {
-  assert(isUInt<N>(Imm) && "Invalid immediate");
+  if (!isUInt<N>(Imm))
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
   return MCDisassembler::Success;
 }

diff  --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 700baa5733b48..6311374d3cc6c 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -548,6 +548,7 @@ def PPCU1ImmAsmOperand : AsmOperandClass {
 def u1imm   : Operand<i32> {
   let PrintMethod = "printU1ImmOperand";
   let ParserMatchClass = PPCU1ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<1>";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
@@ -558,6 +559,7 @@ def PPCU2ImmAsmOperand : AsmOperandClass {
 def u2imm   : Operand<i32> {
   let PrintMethod = "printU2ImmOperand";
   let ParserMatchClass = PPCU2ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<2>";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
@@ -578,6 +580,7 @@ def PPCU3ImmAsmOperand : AsmOperandClass {
 def u3imm   : Operand<i32> {
   let PrintMethod = "printU3ImmOperand";
   let ParserMatchClass = PPCU3ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<3>";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
@@ -588,6 +591,7 @@ def PPCU4ImmAsmOperand : AsmOperandClass {
 def u4imm   : Operand<i32> {
   let PrintMethod = "printU4ImmOperand";
   let ParserMatchClass = PPCU4ImmAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<4>";
   let OperandType = "OPERAND_IMMEDIATE";
 }
 def PPCS5ImmAsmOperand : AsmOperandClass {

diff  --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt
index 3b2e4e2a0161e..783f71cc23454 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31-invalid.txt
@@ -85,3 +85,7 @@
 # pstxv 31, 8589934591(3), 1. However, RA is not zero with R=1
 # CHECK: warning: invalid instruction encoding
 0x04 0x11 0xff 0xff 0xdb 0xe3 0xff 0xff
+
+# xxextractuw 52, 30, 20 (i.e. the immediate 20 is invalid)
+# CHECK: warning: invalid instruction encoding
+0xf2 0x94 0xf2 0x95