[PATCH] D142998: [SVE][codegen] Add test case for a fused multiply-add (NFC)

[Sushant Gokhale via Phabricator via llvm-commits]

sushgokh added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-multiply-add-accumulate.ll:12
+; CHECK-NEXT:    ret
+{
+  %1 = mul <vscale x 2 x i64> %a, %b
----------------
SjoerdMeijer wrote:
> if I am not mistaken, the other patch will change this to 
> 
>   ; CHECK-LABEL: muladd_i64:
>   ; CHECK:       // %bb.0:
>   ; CHECK-NEXT:    ptrue p0.d
>   ; CHECK-NEXT:    mov z2.d, #1 // =0x1
>   ; CHECK-NEXT:    mad z0.d, p0/m, z1.d, z2.d
>   ; CHECK-NEXT:    ret
> 
> (perhaps the immediate is different but that looks irrelevant to me).
> 
> This new codegen looks better, it has 1 mov less, but that is just to return the value. There is no real use of the value, which makes this move visible. Basically what I am saying is that it is unclear what the benefit is.
> 
> But either way, I will repeat my request on the other patch: let's separate things and let this be about instruction selection of 'mad'. This means that we only want to do have 'mad' tests here, and separate out the mla -> mad changes.
I can just commit the tests for mad.

But the changes for D142656 have effect on tests that are currently generating   mla. If I commit tests for mla+mad (as I have done here), comparison will be easier for D142656


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  https://reviews.llvm.org/D142998/new/

https://reviews.llvm.org/D142998