[llvm] 4002576 - AMDGPU/GlobalISel: Partially fix getGenericInstructionUniformity

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2023-01-30T15:47:18-04:00
New Revision: 40025761564bae5b62c38745ed6edc2667419591

URL: https://github.com/llvm/llvm-project/commit/40025761564bae5b62c38745ed6edc2667419591
DIFF: https://github.com/llvm/llvm-project/commit/40025761564bae5b62c38745ed6edc2667419591.diff

LOG: AMDGPU/GlobalISel: Partially fix getGenericInstructionUniformity

This was broken for the common case of instructions which are uniform
if their inputs are uniform. This is broken for control flow intrinsics
since the API currently does not express which result operand is in question.

This generates failures in just about every intrinsic test when uniformity
analysis is performed without this.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index e3f06fe8c3b2..9985fd460acc 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8368,9 +8368,26 @@ SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
   unsigned opcode = MI.getOpcode();
   if (opcode == AMDGPU::G_INTRINSIC ||
       opcode == AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS) {
-    return AMDGPU::isIntrinsicSourceOfDivergence(MI.getIntrinsicID())
-               ? InstructionUniformity::NeverUniform
-               : InstructionUniformity::AlwaysUniform;
+    auto IID = static_cast<Intrinsic::ID>(MI.getIntrinsicID());
+    if (AMDGPU::isIntrinsicSourceOfDivergence(IID))
+      return InstructionUniformity::NeverUniform;
+
+    // FIXME: Get a tablegen table for this.
+    switch (IID) {
+    case Intrinsic::amdgcn_readfirstlane:
+    case Intrinsic::amdgcn_readlane:
+    case Intrinsic::amdgcn_icmp:
+    case Intrinsic::amdgcn_fcmp:
+    case Intrinsic::amdgcn_ballot:
+    case Intrinsic::amdgcn_if_break:
+      return InstructionUniformity::AlwaysUniform;
+    case Intrinsic::amdgcn_if:
+    case Intrinsic::amdgcn_else:
+      // FIXME: Uniform if second result
+      break;
+    }
+
+    return InstructionUniformity::Default;
   }
 
   // Loads from the private and flat address spaces are divergent, because