[PATCH] D142379: [RISCV] Don't explicitly select X0 in select branch comparisons

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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At some point the register coalescer seems to have been improved such
that the workaround added in 450edb0b3766 <https://reviews.llvm.org/rG450edb0b376687dc15c62c1c050e2222de7a2902> is no longer needed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142379

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/float-select-verify.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/shifts.ll

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