[PATCH] D137841: [X86] Reduce unnecessary instregex for AlderlakeP schedule model

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added a comment.

> Do you have any suggestions for scheduler classes that we could add/change to help reduce the number of overrides?

schedtool has tried to reuse same WriteRes and minimize the amount of extra SchedWriteRes.
Here's simplified procedure to auto emit WriteRes and InstRW:

  1. Manually pre associate some schedwrite to it resources so that for each instruction, there's at most 1 schedule write that haven't been associated  with resources. 
  2. For each schedule write that haven’t been associated with schedule resources
  	2.1 Find out instructions which use it as part of default schedule write.
  	2.2 For each instruction, infer Latency, NumMicroOps, Ports so that if this instruction finally use this default schedwrite, then it will get same Lat/NumMicroOps/Ports as we provided in input json.
  	2.3 Find out which schedwrite parameters is the most common one and set this to it.
  3. For rest instructions, since they can’t get correct result with default schedwrite, we need to create a new schedule write, associate it with correct resources, and use InstRW replace instructions main schedwrite with it.

Does overrides have side effect than default one? I think It's not easy to modify default schedreadwrite since it is used by all X86 schedule modes. If we want to change default schedreadwrite to another one, then we may need to update X86 schedmodels.

> After finishing my cleanup of the the conversions I want to look at the old x86 (not BMI) shift / rotate instructions are they aren't setup properly for RMW etc. Have you noticed anything else?

I didn't notice this carefully.


Repository:
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https://reviews.llvm.org/D137841