[llvm] 098e201 - [AArch64][SVE2] Add the SVE2.1 permute vector elements (quadword) instructions
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 10 01:19:18 PST 2022
Author: David Sherwood
Date: 2022-11-10T09:06:57Z
New Revision: 098e20134af5d32a73bd124ca3ce001baa569cab
URL: https://github.com/llvm/llvm-project/commit/098e20134af5d32a73bd124ca3ce001baa569cab
DIFF: https://github.com/llvm/llvm-project/commit/098e20134af5d32a73bd124ca3ce001baa569cab.diff
LOG: [AArch64][SVE2] Add the SVE2.1 permute vector elements (quadword) instructions
This patch adds the assembly/disassembly for the following instructions:
zipq1 : Interleave elements from low halves of each pair of quadword vector segments
zipq2 : Interleave elements from high halves of each pair of quadword vector segments
uzpq1 : Concatenate even elements within each pair of quadword vector segments
uzpq2 : Concatenate odd elements within each pair of quadword vector segments
tblq : Programmable table lookup within each quadword vector segment (zeroing)
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137619
Added:
llvm/test/MC/AArch64/SVE2p1/tblq-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/tblq.s
llvm/test/MC/AArch64/SVE2p1/uzpq1-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/uzpq1.s
llvm/test/MC/AArch64/SVE2p1/uzpq2-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/uzpq2.s
llvm/test/MC/AArch64/SVE2p1/zipq1-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/zipq1.s
llvm/test/MC/AArch64/SVE2p1/zipq2-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/zipq2.s
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 09ccb677ec02..43ea225f0725 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3795,4 +3795,9 @@ defm SMINQV_VPZ : sve2p1_int_reduce_q<0b0110, "sminqv">;
defm UMINQV_VPZ : sve2p1_int_reduce_q<0b0111, "uminqv">;
defm TBXQ_ZZZ : sve2_int_perm_tbx<"tbxq", 0b10, null_frag>;
+defm ZIPQ1_ZZZ : sve2p1_permute_vec_elems_q<0b000, "zipq1">;
+defm ZIPQ2_ZZZ : sve2p1_permute_vec_elems_q<0b001, "zipq2">;
+defm UZPQ1_ZZZ : sve2p1_permute_vec_elems_q<0b010, "uzpq1">;
+defm UZPQ2_ZZZ : sve2p1_permute_vec_elems_q<0b011, "uzpq2">;
+defm TBLQ_ZZZ : sve2p1_tblq<"tblq">;
} // End HasSVE2p1_or_HasSME2p1
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 19b98357bf5e..7f813cd738b9 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -9532,3 +9532,37 @@ multiclass sve2p1_int_reduce_q<bits<4> opc, string mnemonic> {
def _S : sve2p1_int_reduce_q<0b10, opc, mnemonic, ZPR32, "4s">;
def _D : sve2p1_int_reduce_q<0b11, opc, mnemonic, ZPR64, "2d">;
}
+
+
+// SVE permute vector elements (quadwords)
+class sve2p1_permute_vec_elems_q<bits<2> sz, bits<3> opc, string mnemonic,
+ ZPRRegOp zpr_ty, RegisterOperand src1_ty>
+ : I<(outs zpr_ty:$Zd), (ins src1_ty:$Zn, zpr_ty:$Zm),
+ mnemonic, "\t$Zd, $Zn, $Zm",
+ "", []>, Sched<[]> {
+ bits<5> Zd;
+ bits<5> Zn;
+ bits<5> Zm;
+ let Inst{31-24} = 0b01000100;
+ let Inst{23-22} = sz;
+ let Inst{21} = 0b0;
+ let Inst{20-16} = Zm;
+ let Inst{15-13} = 0b111;
+ let Inst{12-10} = opc;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zd;
+}
+
+multiclass sve2p1_permute_vec_elems_q<bits<3> opc, string mnemonic> {
+ def _B : sve2p1_permute_vec_elems_q<0b00, opc, mnemonic, ZPR8, ZPR8>;
+ def _H : sve2p1_permute_vec_elems_q<0b01, opc, mnemonic, ZPR16, ZPR16>;
+ def _S : sve2p1_permute_vec_elems_q<0b10, opc, mnemonic, ZPR32, ZPR32>;
+ def _D : sve2p1_permute_vec_elems_q<0b11, opc, mnemonic, ZPR64, ZPR64>;
+}
+
+multiclass sve2p1_tblq<string mnemonic> {
+ def _B : sve2p1_permute_vec_elems_q<0b00, 0b110, mnemonic, ZPR8, Z_b>;
+ def _H : sve2p1_permute_vec_elems_q<0b01, 0b110, mnemonic, ZPR16, Z_h>;
+ def _S : sve2p1_permute_vec_elems_q<0b10, 0b110, mnemonic, ZPR32, Z_s>;
+ def _D : sve2p1_permute_vec_elems_q<0b11, 0b110, mnemonic, ZPR64, Z_d>;
+}
diff --git a/llvm/test/MC/AArch64/SVE2p1/tblq-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/tblq-diagnostics.s
new file mode 100644
index 000000000000..17c8f9cfe6d4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/tblq-diagnostics.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+tblq z0.b, {z0.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: tblq z0.b, {z0.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+tblq z23.d, {z23.s}, z13.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: tblq z23.d, {z23.s}, z13.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/tblq.s b/llvm/test/MC/AArch64/SVE2p1/tblq.s
new file mode 100644
index 000000000000..33eaf82bc7d3
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/tblq.s
@@ -0,0 +1,114 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+tblq z0.h, {z0.h}, z0.h // 01000100-01000000-11111000-00000000
+// CHECK-INST: tblq z0.h, { z0.h }, z0.h
+// CHECK-ENCODING: [0x00,0xf8,0x40,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4440f800 <unknown>
+
+tblq z21.h, {z10.h}, z21.h // 01000100-01010101-11111001-01010101
+// CHECK-INST: tblq z21.h, { z10.h }, z21.h
+// CHECK-ENCODING: [0x55,0xf9,0x55,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4455f955 <unknown>
+
+tblq z23.h, {z13.h}, z8.h // 01000100-01001000-11111001-10110111
+// CHECK-INST: tblq z23.h, { z13.h }, z8.h
+// CHECK-ENCODING: [0xb7,0xf9,0x48,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4448f9b7 <unknown>
+
+tblq z31.h, {z31.h}, z31.h // 01000100-01011111-11111011-11111111
+// CHECK-INST: tblq z31.h, { z31.h }, z31.h
+// CHECK-ENCODING: [0xff,0xfb,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 445ffbff <unknown>
+
+
+tblq z0.s, {z0.s}, z0.s // 01000100-10000000-11111000-00000000
+// CHECK-INST: tblq z0.s, { z0.s }, z0.s
+// CHECK-ENCODING: [0x00,0xf8,0x80,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4480f800 <unknown>
+
+tblq z21.s, {z10.s}, z21.s // 01000100-10010101-11111001-01010101
+// CHECK-INST: tblq z21.s, { z10.s }, z21.s
+// CHECK-ENCODING: [0x55,0xf9,0x95,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4495f955 <unknown>
+
+tblq z23.s, {z13.s}, z8.s // 01000100-10001000-11111001-10110111
+// CHECK-INST: tblq z23.s, { z13.s }, z8.s
+// CHECK-ENCODING: [0xb7,0xf9,0x88,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4488f9b7 <unknown>
+
+tblq z31.s, {z31.s}, z31.s // 01000100-10011111-11111011-11111111
+// CHECK-INST: tblq z31.s, { z31.s }, z31.s
+// CHECK-ENCODING: [0xff,0xfb,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 449ffbff <unknown>
+
+
+tblq z0.d, {z0.d}, z0.d // 01000100-11000000-11111000-00000000
+// CHECK-INST: tblq z0.d, { z0.d }, z0.d
+// CHECK-ENCODING: [0x00,0xf8,0xc0,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c0f800 <unknown>
+
+tblq z21.d, {z10.d}, z21.d // 01000100-11010101-11111001-01010101
+// CHECK-INST: tblq z21.d, { z10.d }, z21.d
+// CHECK-ENCODING: [0x55,0xf9,0xd5,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44d5f955 <unknown>
+
+tblq z23.d, {z13.d}, z8.d // 01000100-11001000-11111001-10110111
+// CHECK-INST: tblq z23.d, { z13.d }, z8.d
+// CHECK-ENCODING: [0xb7,0xf9,0xc8,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c8f9b7 <unknown>
+
+tblq z31.d, {z31.d}, z31.d // 01000100-11011111-11111011-11111111
+// CHECK-INST: tblq z31.d, { z31.d }, z31.d
+// CHECK-ENCODING: [0xff,0xfb,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44dffbff <unknown>
+
+
+tblq z0.b, {z0.b}, z0.b // 01000100-00000000-11111000-00000000
+// CHECK-INST: tblq z0.b, { z0.b }, z0.b
+// CHECK-ENCODING: [0x00,0xf8,0x00,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4400f800 <unknown>
+
+tblq z21.b, {z10.b}, z21.b // 01000100-00010101-11111001-01010101
+// CHECK-INST: tblq z21.b, { z10.b }, z21.b
+// CHECK-ENCODING: [0x55,0xf9,0x15,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4415f955 <unknown>
+
+tblq z23.b, {z13.b}, z8.b // 01000100-00001000-11111001-10110111
+// CHECK-INST: tblq z23.b, { z13.b }, z8.b
+// CHECK-ENCODING: [0xb7,0xf9,0x08,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4408f9b7 <unknown>
+
+tblq z31.b, {z31.b}, z31.b // 01000100-00011111-11111011-11111111
+// CHECK-INST: tblq z31.b, { z31.b }, z31.b
+// CHECK-ENCODING: [0xff,0xfb,0x1f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 441ffbff <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2p1/uzpq1-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/uzpq1-diagnostics.s
new file mode 100644
index 000000000000..fd4986caa098
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uzpq1-diagnostics.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid register suffixes
+
+uzpq1 z0.h, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uzpq1 z0.h, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uzpq1 z0.d, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uzpq1 z0.d, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/uzpq1.s b/llvm/test/MC/AArch64/SVE2p1/uzpq1.s
new file mode 100644
index 000000000000..22ebc9ed912b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uzpq1.s
@@ -0,0 +1,115 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uzpq1 z0.h, z0.h, z0.h // 01000100-01000000-11101000-00000000
+// CHECK-INST: uzpq1 z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xe8,0x40,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4440e800 <unknown>
+
+uzpq1 z21.h, z10.h, z21.h // 01000100-01010101-11101001-01010101
+// CHECK-INST: uzpq1 z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xe9,0x55,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4455e955 <unknown>
+
+uzpq1 z23.h, z13.h, z8.h // 01000100-01001000-11101001-10110111
+// CHECK-INST: uzpq1 z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xe9,0x48,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4448e9b7 <unknown>
+
+uzpq1 z31.h, z31.h, z31.h // 01000100-01011111-11101011-11111111
+// CHECK-INST: uzpq1 z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xeb,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 445febff <unknown>
+
+
+uzpq1 z0.s, z0.s, z0.s // 01000100-10000000-11101000-00000000
+// CHECK-INST: uzpq1 z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xe8,0x80,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4480e800 <unknown>
+
+uzpq1 z21.s, z10.s, z21.s // 01000100-10010101-11101001-01010101
+// CHECK-INST: uzpq1 z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0xe9,0x95,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4495e955 <unknown>
+
+uzpq1 z23.s, z13.s, z8.s // 01000100-10001000-11101001-10110111
+// CHECK-INST: uzpq1 z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0xe9,0x88,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4488e9b7 <unknown>
+
+uzpq1 z31.s, z31.s, z31.s // 01000100-10011111-11101011-11111111
+// CHECK-INST: uzpq1 z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0xeb,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 449febff <unknown>
+
+
+uzpq1 z0.d, z0.d, z0.d // 01000100-11000000-11101000-00000000
+// CHECK-INST: uzpq1 z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xe8,0xc0,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c0e800 <unknown>
+
+uzpq1 z21.d, z10.d, z21.d // 01000100-11010101-11101001-01010101
+// CHECK-INST: uzpq1 z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0xe9,0xd5,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44d5e955 <unknown>
+
+uzpq1 z23.d, z13.d, z8.d // 01000100-11001000-11101001-10110111
+// CHECK-INST: uzpq1 z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0xe9,0xc8,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c8e9b7 <unknown>
+
+uzpq1 z31.d, z31.d, z31.d // 01000100-11011111-11101011-11111111
+// CHECK-INST: uzpq1 z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0xeb,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44dfebff <unknown>
+
+
+uzpq1 z0.b, z0.b, z0.b // 01000100-00000000-11101000-00000000
+// CHECK-INST: uzpq1 z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xe8,0x00,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4400e800 <unknown>
+
+uzpq1 z21.b, z10.b, z21.b // 01000100-00010101-11101001-01010101
+// CHECK-INST: uzpq1 z21.b, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0xe9,0x15,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4415e955 <unknown>
+
+uzpq1 z23.b, z13.b, z8.b // 01000100-00001000-11101001-10110111
+// CHECK-INST: uzpq1 z23.b, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0xe9,0x08,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4408e9b7 <unknown>
+
+uzpq1 z31.b, z31.b, z31.b // 01000100-00011111-11101011-11111111
+// CHECK-INST: uzpq1 z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0xeb,0x1f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 441febff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/uzpq2-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/uzpq2-diagnostics.s
new file mode 100644
index 000000000000..01716d932347
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uzpq2-diagnostics.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid register suffixes
+
+uzpq2 z0.h, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uzpq2 z0.h, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uzpq2 z0.d, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uzpq2 z0.d, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/uzpq2.s b/llvm/test/MC/AArch64/SVE2p1/uzpq2.s
new file mode 100644
index 000000000000..2d271754d021
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/uzpq2.s
@@ -0,0 +1,115 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uzpq2 z0.h, z0.h, z0.h // 01000100-01000000-11101100-00000000
+// CHECK-INST: uzpq2 z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xec,0x40,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4440ec00 <unknown>
+
+uzpq2 z21.h, z10.h, z21.h // 01000100-01010101-11101101-01010101
+// CHECK-INST: uzpq2 z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xed,0x55,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4455ed55 <unknown>
+
+uzpq2 z23.h, z13.h, z8.h // 01000100-01001000-11101101-10110111
+// CHECK-INST: uzpq2 z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xed,0x48,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4448edb7 <unknown>
+
+uzpq2 z31.h, z31.h, z31.h // 01000100-01011111-11101111-11111111
+// CHECK-INST: uzpq2 z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xef,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 445fefff <unknown>
+
+
+uzpq2 z0.s, z0.s, z0.s // 01000100-10000000-11101100-00000000
+// CHECK-INST: uzpq2 z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xec,0x80,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4480ec00 <unknown>
+
+uzpq2 z21.s, z10.s, z21.s // 01000100-10010101-11101101-01010101
+// CHECK-INST: uzpq2 z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0xed,0x95,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4495ed55 <unknown>
+
+uzpq2 z23.s, z13.s, z8.s // 01000100-10001000-11101101-10110111
+// CHECK-INST: uzpq2 z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0xed,0x88,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4488edb7 <unknown>
+
+uzpq2 z31.s, z31.s, z31.s // 01000100-10011111-11101111-11111111
+// CHECK-INST: uzpq2 z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0xef,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 449fefff <unknown>
+
+
+uzpq2 z0.d, z0.d, z0.d // 01000100-11000000-11101100-00000000
+// CHECK-INST: uzpq2 z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xec,0xc0,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c0ec00 <unknown>
+
+uzpq2 z21.d, z10.d, z21.d // 01000100-11010101-11101101-01010101
+// CHECK-INST: uzpq2 z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0xed,0xd5,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44d5ed55 <unknown>
+
+uzpq2 z23.d, z13.d, z8.d // 01000100-11001000-11101101-10110111
+// CHECK-INST: uzpq2 z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0xed,0xc8,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c8edb7 <unknown>
+
+uzpq2 z31.d, z31.d, z31.d // 01000100-11011111-11101111-11111111
+// CHECK-INST: uzpq2 z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0xef,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44dfefff <unknown>
+
+
+uzpq2 z0.b, z0.b, z0.b // 01000100-00000000-11101100-00000000
+// CHECK-INST: uzpq2 z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xec,0x00,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4400ec00 <unknown>
+
+uzpq2 z21.b, z10.b, z21.b // 01000100-00010101-11101101-01010101
+// CHECK-INST: uzpq2 z21.b, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0xed,0x15,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4415ed55 <unknown>
+
+uzpq2 z23.b, z13.b, z8.b // 01000100-00001000-11101101-10110111
+// CHECK-INST: uzpq2 z23.b, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0xed,0x08,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4408edb7 <unknown>
+
+uzpq2 z31.b, z31.b, z31.b // 01000100-00011111-11101111-11111111
+// CHECK-INST: uzpq2 z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0xef,0x1f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 441fefff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/zipq1-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/zipq1-diagnostics.s
new file mode 100644
index 000000000000..94a4be1be28f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/zipq1-diagnostics.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid register suffixes
+
+zipq1 z0.h, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: zipq1 z0.h, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+zipq1 z0.d, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: zipq1 z0.d, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/zipq1.s b/llvm/test/MC/AArch64/SVE2p1/zipq1.s
new file mode 100644
index 000000000000..97a60d56357b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/zipq1.s
@@ -0,0 +1,115 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+zipq1 z0.h, z0.h, z0.h // 01000100-01000000-11100000-00000000
+// CHECK-INST: zipq1 z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xe0,0x40,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4440e000 <unknown>
+
+zipq1 z21.h, z10.h, z21.h // 01000100-01010101-11100001-01010101
+// CHECK-INST: zipq1 z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xe1,0x55,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4455e155 <unknown>
+
+zipq1 z23.h, z13.h, z8.h // 01000100-01001000-11100001-10110111
+// CHECK-INST: zipq1 z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xe1,0x48,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4448e1b7 <unknown>
+
+zipq1 z31.h, z31.h, z31.h // 01000100-01011111-11100011-11111111
+// CHECK-INST: zipq1 z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xe3,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 445fe3ff <unknown>
+
+
+zipq1 z0.s, z0.s, z0.s // 01000100-10000000-11100000-00000000
+// CHECK-INST: zipq1 z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xe0,0x80,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4480e000 <unknown>
+
+zipq1 z21.s, z10.s, z21.s // 01000100-10010101-11100001-01010101
+// CHECK-INST: zipq1 z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0xe1,0x95,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4495e155 <unknown>
+
+zipq1 z23.s, z13.s, z8.s // 01000100-10001000-11100001-10110111
+// CHECK-INST: zipq1 z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0xe1,0x88,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4488e1b7 <unknown>
+
+zipq1 z31.s, z31.s, z31.s // 01000100-10011111-11100011-11111111
+// CHECK-INST: zipq1 z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0xe3,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 449fe3ff <unknown>
+
+
+zipq1 z0.d, z0.d, z0.d // 01000100-11000000-11100000-00000000
+// CHECK-INST: zipq1 z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xe0,0xc0,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c0e000 <unknown>
+
+zipq1 z21.d, z10.d, z21.d // 01000100-11010101-11100001-01010101
+// CHECK-INST: zipq1 z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0xe1,0xd5,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44d5e155 <unknown>
+
+zipq1 z23.d, z13.d, z8.d // 01000100-11001000-11100001-10110111
+// CHECK-INST: zipq1 z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0xe1,0xc8,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c8e1b7 <unknown>
+
+zipq1 z31.d, z31.d, z31.d // 01000100-11011111-11100011-11111111
+// CHECK-INST: zipq1 z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0xe3,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44dfe3ff <unknown>
+
+
+zipq1 z0.b, z0.b, z0.b // 01000100-00000000-11100000-00000000
+// CHECK-INST: zipq1 z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xe0,0x00,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4400e000 <unknown>
+
+zipq1 z21.b, z10.b, z21.b // 01000100-00010101-11100001-01010101
+// CHECK-INST: zipq1 z21.b, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0xe1,0x15,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4415e155 <unknown>
+
+zipq1 z23.b, z13.b, z8.b // 01000100-00001000-11100001-10110111
+// CHECK-INST: zipq1 z23.b, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0xe1,0x08,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4408e1b7 <unknown>
+
+zipq1 z31.b, z31.b, z31.b // 01000100-00011111-11100011-11111111
+// CHECK-INST: zipq1 z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0xe3,0x1f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 441fe3ff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/zipq2-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/zipq2-diagnostics.s
new file mode 100644
index 000000000000..c9b150be05da
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/zipq2-diagnostics.s
@@ -0,0 +1,14 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid register suffixes
+
+zipq2 z0.h, z0.h, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: zipq2 z0.h, z0.h, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+zipq2 z0.d, z0.s, z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: zipq2 z0.d, z0.s, z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/zipq2.s b/llvm/test/MC/AArch64/SVE2p1/zipq2.s
new file mode 100644
index 000000000000..fc75bbf9f622
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/zipq2.s
@@ -0,0 +1,115 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+zipq2 z0.h, z0.h, z0.h // 01000100-01000000-11100100-00000000
+// CHECK-INST: zipq2 z0.h, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xe4,0x40,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4440e400 <unknown>
+
+zipq2 z21.h, z10.h, z21.h // 01000100-01010101-11100101-01010101
+// CHECK-INST: zipq2 z21.h, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xe5,0x55,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4455e555 <unknown>
+
+zipq2 z23.h, z13.h, z8.h // 01000100-01001000-11100101-10110111
+// CHECK-INST: zipq2 z23.h, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xe5,0x48,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4448e5b7 <unknown>
+
+zipq2 z31.h, z31.h, z31.h // 01000100-01011111-11100111-11111111
+// CHECK-INST: zipq2 z31.h, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xe7,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 445fe7ff <unknown>
+
+
+zipq2 z0.s, z0.s, z0.s // 01000100-10000000-11100100-00000000
+// CHECK-INST: zipq2 z0.s, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xe4,0x80,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4480e400 <unknown>
+
+zipq2 z21.s, z10.s, z21.s // 01000100-10010101-11100101-01010101
+// CHECK-INST: zipq2 z21.s, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0xe5,0x95,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4495e555 <unknown>
+
+zipq2 z23.s, z13.s, z8.s // 01000100-10001000-11100101-10110111
+// CHECK-INST: zipq2 z23.s, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0xe5,0x88,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4488e5b7 <unknown>
+
+zipq2 z31.s, z31.s, z31.s // 01000100-10011111-11100111-11111111
+// CHECK-INST: zipq2 z31.s, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0xe7,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 449fe7ff <unknown>
+
+
+zipq2 z0.d, z0.d, z0.d // 01000100-11000000-11100100-00000000
+// CHECK-INST: zipq2 z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xe4,0xc0,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c0e400 <unknown>
+
+zipq2 z21.d, z10.d, z21.d // 01000100-11010101-11100101-01010101
+// CHECK-INST: zipq2 z21.d, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0xe5,0xd5,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44d5e555 <unknown>
+
+zipq2 z23.d, z13.d, z8.d // 01000100-11001000-11100101-10110111
+// CHECK-INST: zipq2 z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0xe5,0xc8,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44c8e5b7 <unknown>
+
+zipq2 z31.d, z31.d, z31.d // 01000100-11011111-11100111-11111111
+// CHECK-INST: zipq2 z31.d, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0xe7,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 44dfe7ff <unknown>
+
+
+zipq2 z0.b, z0.b, z0.b // 01000100-00000000-11100100-00000000
+// CHECK-INST: zipq2 z0.b, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xe4,0x00,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4400e400 <unknown>
+
+zipq2 z21.b, z10.b, z21.b // 01000100-00010101-11100101-01010101
+// CHECK-INST: zipq2 z21.b, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0xe5,0x15,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4415e555 <unknown>
+
+zipq2 z23.b, z13.b, z8.b // 01000100-00001000-11100101-10110111
+// CHECK-INST: zipq2 z23.b, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0xe5,0x08,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 4408e5b7 <unknown>
+
+zipq2 z31.b, z31.b, z31.b // 01000100-00011111-11100111-11111111
+// CHECK-INST: zipq2 z31.b, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0xe7,0x1f,0x44]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 441fe7ff <unknown>
+
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