[PATCH] D132358: [RISCV][ISel] improved compressed instruction use

[Dmitry via Phabricator via llvm-commits]

dybv-sc added a comment.

So, after more running more spec tests in different modes (train and ref) on different RISCV boards (SiFive and THead) I got mixed results on performance. Performance increase on number on tests was insignificant while on other there was a slight decrease. On average performance declined by 0.5%. On the other hand, size reduction can be seen uniformly among all tests. On average it is 20 less bytes or 0.04% of size reduction. I think these amounts can't justify the performance cost.
Considering that some performance reductions are platform specific (like the one I mentioned in previous comment) and rely on internal architecture features, it is not seem possible to come up with general solution here. And more specialized ones will require more time and effort. And possible 0.04% code size reduction just not worth it.
What do you think?


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https://reviews.llvm.org/D132358