[PATCH] D134755: [RISCV] Extend strided load/store pattern matching to non-loop cases

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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The motivation here is to enable a change I'm exploring in vectorizer to prefer base + offset_vector addressing for scatter/gather.  The form the vectorizer would end up emitting would be a gep whose vector operand is an add of the scalar IV (splated) and the index vector.  This change makes sure we can recognize that pattern as well as the current code structure.  As a side effect, it might improve scatter/gathers from other sources.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134755

Files:
  llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll

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