[PATCH] D130251: [DAGCombine] Mask doesn't have to be (EltSize - 1) exactly when combining rotation

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7304
+    unsigned Bits = Log2_64(EltSize);
+    APInt DemandedBits = APInt::getLowBitsSet(EltSize, Bits);
+    if (SDValue Inner =
----------------
I'm only guessing but you might need to use Neg.getScalarValueSizeInBits instead of EltSize - it might be that the shift amount type doesn't match the result type


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7324
+  if (MaskLoBits) {
+    APInt DemandedBits = APInt::getLowBitsSet(EltSize, MaskLoBits);
+    if (SDValue Inner =
----------------
Pos.getScalarValueSizeInBits instead of EltSize


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130251/new/

https://reviews.llvm.org/D130251