[PATCH] D129179: [RISCV] Extend use of SHXADD instructions in RVV spill/reload code.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan marked 2 inline comments as done.
jacquesguan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1809
+    uint32_t ShiftAmount;
+    if (NumOfVReg % 3 == 0) {
+      Opc = RISCV::SH1ADD;
----------------
craig.topper wrote:
> `NumOfVReg % 3 == 0` when we really matched the `(NumOfVReg % 9 == 0 && isPowerOf2_64(NumOfVReg / 9)` case. Any number divisible by 9 is also divisible by 3.
Done, thanks.


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Comment at: llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll:238
+; ZBA-NEXT:    slli a0, a0, 2
+; ZBA-NEXT:    sh1add a0, a0, a0
+; ZBA-NEXT:    sub sp, sp, a0
----------------
craig.topper wrote:
> Should we be testing more than sh1add?
Done, I add cases of sh2add and sh3add.


Repository:
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  https://reviews.llvm.org/D129179/new/

https://reviews.llvm.org/D129179