[llvm] 049e107 - [NFC][SVE] Add more tests of vector compares and selects taking an immediate operand.
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 27 10:23:51 PDT 2022
Author: Paul Walker
Date: 2022-06-27T18:22:40+01:00
New Revision: 049e107139a3c3ff718586e270c79e206e2ba124
URL: https://github.com/llvm/llvm-project/commit/049e107139a3c3ff718586e270c79e206e2ba124
DIFF: https://github.com/llvm/llvm-project/commit/049e107139a3c3ff718586e270c79e206e2ba124.diff
LOG: [NFC][SVE] Add more tests of vector compares and selects taking an immediate operand.
Increases coverage of predicated compares (int and fp) along with
predicated zeroing of active floating point lanes.
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-fcmp.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-fcmp.ll b/llvm/test/CodeGen/AArch64/sve-fcmp.ll
index 6e966d1dccc29..b495bdf510d78 100644
--- a/llvm/test/CodeGen/AArch64/sve-fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fcmp.ll
@@ -432,3 +432,63 @@ define <vscale x 4 x i1> @une_zero(<vscale x 4 x float> %x) {
%y = fcmp une <vscale x 4 x float> %x, zeroinitializer
ret <vscale x 4 x i1> %y
}
+define <vscale x 8 x i1> @oeq_zero_pred(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) {
+; CHECK-LABEL: oeq_zero_pred:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #0 // =0x0
+; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: ret
+ %y = fcmp oeq <vscale x 8 x half> %x, zeroinitializer
+ %z = and <vscale x 8 x i1> %pg, %y
+ ret <vscale x 8 x i1> %z
+}
+define <vscale x 4 x i1> @ogt_zero_pred(<vscale x 4 x i1> %pg, <vscale x 4 x half> %x) {
+; CHECK-LABEL: ogt_zero_pred:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #0 // =0x0
+; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: ret
+ %y = fcmp ogt <vscale x 4 x half> %x, zeroinitializer
+ %z = and <vscale x 4 x i1> %pg, %y
+ ret <vscale x 4 x i1> %z
+}
+define <vscale x 2 x i1> @oge_zero_pred(<vscale x 2 x i1> %pg, <vscale x 2 x half> %x) {
+; CHECK-LABEL: oge_zero_pred:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #0 // =0x0
+; CHECK-NEXT: fcmge p0.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: ret
+ %y = fcmp oge <vscale x 2 x half> %x, zeroinitializer
+ %z = and <vscale x 2 x i1> %pg, %y
+ ret <vscale x 2 x i1> %z
+}
+define <vscale x 4 x i1> @olt_zero_pred(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) {
+; CHECK-LABEL: olt_zero_pred:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: fcmgt p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT: ret
+ %y = fcmp olt <vscale x 4 x float> %x, zeroinitializer
+ %z = and <vscale x 4 x i1> %pg, %y
+ ret <vscale x 4 x i1> %z
+}
+define <vscale x 2 x i1> @ole_zero_pred(<vscale x 2 x i1> %pg, <vscale x 2 x float> %x) {
+; CHECK-LABEL: ole_zero_pred:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: fcmge p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT: ret
+ %y = fcmp ole <vscale x 2 x float> %x, zeroinitializer
+ %z = and <vscale x 2 x i1> %pg, %y
+ ret <vscale x 2 x i1> %z
+}
+define <vscale x 2 x i1> @une_zero_pred(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
+; CHECK-LABEL: une_zero_pred:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.d, #0 // =0x0
+; CHECK-NEXT: fcmne p0.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: ret
+ %y = fcmp une <vscale x 2 x double> %x, zeroinitializer
+ %z = and <vscale x 2 x i1> %pg, %y
+ ret <vscale x 2 x i1> %z
+}
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
index 702249e4f606f..a5bcb9d688ba2 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
@@ -1096,6 +1096,126 @@ define <vscale x 4 x i1> @predicated_icmp_unknown_rhs(<vscale x 4 x i1> %a, <vsc
ret <vscale x 4 x i1> %and
}
+define <vscale x 16 x i1> @predicated_icmp_eq_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: predicated_icmp_eq_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.b, #0 // =0x0
+; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 0, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %icmp = icmp eq <vscale x 16 x i8> %b, %imm
+ %and = and <vscale x 16 x i1> %a, %icmp
+ ret <vscale x 16 x i1> %and
+}
+
+define <vscale x 8 x i1> @predicated_icmp_ne_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: predicated_icmp_ne_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #-16 // =0xfffffffffffffff0
+; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -16, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %icmp = icmp ne <vscale x 8 x i16> %b, %imm
+ %and = and <vscale x 8 x i1> %a, %icmp
+ ret <vscale x 8 x i1> %and
+}
+
+define <vscale x 4 x i1> @predicated_icmp_sge_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: predicated_icmp_sge_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.s, #1 // =0x1
+; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %icmp = icmp sge <vscale x 4 x i32> %b, %imm
+ %and = and <vscale x 4 x i1> %a, %icmp
+ ret <vscale x 4 x i1> %and
+}
+
+define <vscale x 2 x i1> @predicated_icmp_sgt_imm(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: predicated_icmp_sgt_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.d, #2 // =0x2
+; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 2, i64 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %icmp = icmp sgt <vscale x 2 x i64> %b, %imm
+ %and = and <vscale x 2 x i1> %a, %icmp
+ ret <vscale x 2 x i1> %and
+}
+
+define <vscale x 16 x i1> @predicated_icmp_sle_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: predicated_icmp_sle_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.b, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: cmpge p0.b, p0/z, z1.b, z0.b
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 -1, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %icmp = icmp sle <vscale x 16 x i8> %b, %imm
+ %and = and <vscale x 16 x i1> %a, %icmp
+ ret <vscale x 16 x i1> %and
+}
+
+define <vscale x 8 x i1> @predicated_icmp_slt_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: predicated_icmp_slt_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #-2 // =0xfffffffffffffffe
+; CHECK-NEXT: cmpgt p0.h, p0/z, z1.h, z0.h
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -2, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %icmp = icmp slt <vscale x 8 x i16> %b, %imm
+ %and = and <vscale x 8 x i1> %a, %icmp
+ ret <vscale x 8 x i1> %and
+}
+
+define <vscale x 4 x i1> @predicated_icmp_uge_imm(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: predicated_icmp_uge_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.s, #1 // =0x1
+; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %icmp = icmp uge <vscale x 4 x i32> %b, %imm
+ %and = and <vscale x 4 x i1> %a, %icmp
+ ret <vscale x 4 x i1> %and
+}
+
+define <vscale x 2 x i1> @predicated_icmp_ugt_imm(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: predicated_icmp_ugt_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.d, #2 // =0x2
+; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 2, i64 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %icmp = icmp ugt <vscale x 2 x i64> %b, %imm
+ %and = and <vscale x 2 x i1> %a, %icmp
+ ret <vscale x 2 x i1> %and
+}
+
+define <vscale x 16 x i1> @predicated_icmp_ule_imm(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: predicated_icmp_ule_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.b, #3 // =0x3
+; CHECK-NEXT: cmphs p0.b, p0/z, z1.b, z0.b
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i64 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+ %icmp = icmp ule <vscale x 16 x i8> %b, %imm
+ %and = and <vscale x 16 x i1> %a, %icmp
+ ret <vscale x 16 x i1> %and
+}
+
+define <vscale x 8 x i1> @predicated_icmp_ult_imm(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: predicated_icmp_ult_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #127 // =0x7f
+; CHECK-NEXT: cmphi p0.h, p0/z, z1.h, z0.h
+; CHECK-NEXT: ret
+ %imm = shufflevector <vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 127, i64 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+ %icmp = icmp ult <vscale x 8 x i16> %b, %imm
+ %and = and <vscale x 8 x i1> %a, %icmp
+ ret <vscale x 8 x i1> %and
+}
+
declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
diff --git a/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll b/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
index d74a59be91bae..5b65c1ab9ab73 100644
--- a/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
@@ -308,6 +308,66 @@ define <vscale x 2 x i64> @sel_merge_64_zero(<vscale x 2 x i1> %p, <vscale x 2 x
ret <vscale x 2 x i64> %sel
}
+define <vscale x 8 x half> @sel_merge_nxv8f16_zero(<vscale x 8 x i1> %p, <vscale x 8 x half> %in) {
+; CHECK-LABEL: sel_merge_nxv8f16_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #0 // =0x0
+; CHECK-NEXT: mov z0.h, p0/m, z1.h
+; CHECK-NEXT: ret
+%sel = select <vscale x 8 x i1> %p, <vscale x 8 x half> zeroinitializer, <vscale x 8 x half> %in
+ret <vscale x 8 x half> %sel
+}
+
+define <vscale x 4 x half> @sel_merge_nx4f16_zero(<vscale x 4 x i1> %p, <vscale x 4 x half> %in) {
+; CHECK-LABEL: sel_merge_nx4f16_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #0 // =0x0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+%sel = select <vscale x 4 x i1> %p, <vscale x 4 x half> zeroinitializer, <vscale x 4 x half> %in
+ret <vscale x 4 x half> %sel
+}
+
+define <vscale x 2 x half> @sel_merge_nx2f16_zero(<vscale x 2 x i1> %p, <vscale x 2 x half> %in) {
+; CHECK-LABEL: sel_merge_nx2f16_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.h, #0 // =0x0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x half> zeroinitializer, <vscale x 2 x half> %in
+ret <vscale x 2 x half> %sel
+}
+
+define <vscale x 4 x float> @sel_merge_nx4f32_zero(<vscale x 4 x i1> %p, <vscale x 4 x float> %in) {
+; CHECK-LABEL: sel_merge_nx4f32_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: mov z0.s, p0/m, z1.s
+; CHECK-NEXT: ret
+%sel = select <vscale x 4 x i1> %p, <vscale x 4 x float> zeroinitializer, <vscale x 4 x float> %in
+ret <vscale x 4 x float> %sel
+}
+
+define <vscale x 2 x float> @sel_merge_nx2f32_zero(<vscale x 2 x i1> %p, <vscale x 2 x float> %in) {
+; CHECK-LABEL: sel_merge_nx2f32_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.s, #0 // =0x0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x float> zeroinitializer, <vscale x 2 x float> %in
+ret <vscale x 2 x float> %sel
+}
+
+define <vscale x 2 x double> @sel_merge_nx2f64_zero(<vscale x 2 x i1> %p, <vscale x 2 x double> %in) {
+; CHECK-LABEL: sel_merge_nx2f64_zero:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov z1.d, #0 // =0x0
+; CHECK-NEXT: mov z0.d, p0/m, z1.d
+; CHECK-NEXT: ret
+%sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> zeroinitializer, <vscale x 2 x double> %in
+ret <vscale x 2 x double> %sel
+}
+
define <vscale x 8 x i16> @sel_merge_16_shifted(<vscale x 8 x i1> %p, <vscale x 8 x i16> %in) {
; CHECK-LABEL: sel_merge_16_shifted:
; CHECK: // %bb.0:
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