[PATCH] D127095: [llvm][CodeGen] Add a default implementation to check whether two memory accesses are trivially disjoint

Xiaoqiang Xu via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 6 19:28:41 PDT 2022


csstormq added a comment.

In D127095#3560947 <https://reviews.llvm.org/D127095#3560947>, @efriedma wrote:

> Most of the existing target-independent code related to memoperand aliasing is in MachineInstr::mayAlias (specifically the MemOperandsHaveAlias helper).  Is there some reason you can't just extend that?

In our case, we want to do the following two things.

First, in the overloaded SelectionDAGISel::PostprocessISelDAG, we want to break unnecessary chain dependencies between load and store instructions, represented as MachineSDNode, for having a positive affect on the result of pre-RA scheduler.

I am not sure whether it's suit to construct temporary variables of MachineInstr here just for enabling to invoke the MachineInstr::mayAlias. So I provide an individual function, called areMemAccessesTriviallyDisjoint, to finish the same work. This function does not care whether both instructions are MachineInstr or not. That's why the parameters of it are machine memory operands.

Second, because the result of pre-RA scheduler whicherver we choose is not exactly what we expected, we write a machine pass to adjust slightly the sequence between load and store instructions, represented as MachineInstr. Here, it is natural to invoke MachineInstr::mayAlias. To finish our work, I add a default implementation for TargetInstrInfo::areMemAccessesTriviallyDisjoint as the code shown. So the users of invoking MachineInstr::mayAlias will benefit fromt it by default.

That's all.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127095/new/

https://reviews.llvm.org/D127095



More information about the llvm-commits mailing list