[PATCH] D126854: [RISCV] Define risc-v's own register class to model FP Register.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h:232
+    Type *ScalarTy = Ty->getScalarType();
+    if ((ScalarTy->isBFloatTy() && ST->hasStdExtZfh()) ||
+        (ScalarTy->isFloatTy() && ST->hasStdExtF()) ||
----------------
Checking `isHalfTy` rather than `isBFloatTy` here, `isBFloatTy` is `bfloat` type and we don't support that in any extension yet.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D126854/new/

https://reviews.llvm.org/D126854