[llvm] 808c33a - [RISCV][AArch64] Pre-commit tests for D124711. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-04-30T10:59:20-07:00
New Revision: 808c33ace547f0c71fd256e94fedf879f5e89728

URL: https://github.com/llvm/llvm-project/commit/808c33ace547f0c71fd256e94fedf879f5e89728
DIFF: https://github.com/llvm/llvm-project/commit/808c33ace547f0c71fd256e94fedf879f5e89728.diff

LOG: [RISCV][AArch64] Pre-commit tests for D124711. NFC

Added: 
    llvm/test/CodeGen/AArch64/pr55201.ll
    llvm/test/CodeGen/RISCV/pr55201.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/pr55201.ll b/llvm/test/CodeGen/AArch64/pr55201.ll
new file mode 100644
index 0000000000000..52f7cc0b708d5
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr55201.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
+
+define i32 @f(i32 %x) {
+; CHECK-LABEL: f:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ror w8, w0, #27
+; CHECK-NEXT:    orr w0, w8, #0x20
+; CHECK-NEXT:    ret
+  %or1 = or i32 %x, 1
+  %sh1 = shl i32 %or1, 5
+  %sh2 = lshr i32 %x, 27
+  %1 = and i32 %sh2, 1
+  %r = or i32 %sh1, %1
+  ret i32 %r
+}

diff  --git a/llvm/test/CodeGen/RISCV/pr55201.ll b/llvm/test/CodeGen/RISCV/pr55201.ll
new file mode 100644
index 0000000000000..7dc9c378a14a1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr55201.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s
+
+define i32 @f(i32 %x) {
+; CHECK-LABEL: f:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rori a0, a0, 27
+; CHECK-NEXT:    ori a0, a0, 32
+; CHECK-NEXT:    ret
+  %or1 = or i32 %x, 1
+  %sh1 = shl i32 %or1, 5
+  %sh2 = lshr i32 %x, 27
+  %1 = and i32 %sh2, 1
+  %r = or i32 %sh1, %1
+  ret i32 %r
+}