[llvm] 3f3ff0e - Mips/GlobalISel: Remove test IR sections and regenerate checks
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 11 16:44:39 PDT 2022
Author: Matt Arsenault
Date: 2022-04-11T19:43:37-04:00
New Revision: 3f3ff0e4309ac317ebea3e44188751451b88862f
URL: https://github.com/llvm/llvm-project/commit/3f3ff0e4309ac317ebea3e44188751451b88862f
DIFF: https://github.com/llvm/llvm-project/commit/3f3ff0e4309ac317ebea3e44188751451b88862f.diff
LOG: Mips/GlobalISel: Remove test IR sections and regenerate checks
Added:
Modified:
llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
index 340fda34e95c7..c58b8541d1ee1 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir
@@ -1,13 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
---- |
-
- define void @load_i32(i32* %ptr) {entry: ret void}
- define void @load_i64(i64* %ptr) {entry: ret void}
- define void @load_float(float* %ptr) {entry: ret void}
- define void @load_double(double* %ptr) {entry: ret void}
-
-...
---
name: load_i32
alignment: 4
@@ -18,12 +10,13 @@ body: |
; MIPS32-LABEL: name: load_i32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
- %1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
+ %1:_(s32) = G_LOAD %0(p0) :: (load (s32))
$v0 = COPY %1(s32)
RetRA implicit $v0
@@ -38,14 +31,15 @@ body: |
; MIPS32-LABEL: name: load_i64
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.ptr)
- ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
- ; MIPS32: $v0 = COPY [[UV]](s32)
- ; MIPS32: $v1 = COPY [[UV1]](s32)
- ; MIPS32: RetRA implicit $v0, implicit $v1
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; MIPS32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
+ ; MIPS32-NEXT: $v0 = COPY [[UV]](s32)
+ ; MIPS32-NEXT: $v1 = COPY [[UV1]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
- %1:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
+ %1:_(s64) = G_LOAD %0(p0) :: (load (s64))
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
@@ -62,12 +56,13 @@ body: |
; MIPS32-LABEL: name: load_float
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.ptr)
- ; MIPS32: $f0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $f0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+ ; MIPS32-NEXT: $f0 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $f0
%0:_(p0) = COPY $a0
- %1:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
+ %1:_(s32) = G_LOAD %0(p0) :: (load (s32))
$f0 = COPY %1(s32)
RetRA implicit $f0
@@ -82,12 +77,13 @@ body: |
; MIPS32-LABEL: name: load_double
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.ptr)
- ; MIPS32: $d0 = COPY [[LOAD]](s64)
- ; MIPS32: RetRA implicit $d0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+ ; MIPS32-NEXT: $d0 = COPY [[LOAD]](s64)
+ ; MIPS32-NEXT: RetRA implicit $d0
%0:_(p0) = COPY $a0
- %1:_(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
+ %1:_(s64) = G_LOAD %0(p0) :: (load (s64))
$d0 = COPY %1(s64)
RetRA implicit $d0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
index cd83d2f797951..636bf35f44c23 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
@@ -1,15 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
---- |
-
- define void @load_store_v16i8(<16 x i8>* %a, <16 x i8>* %b) { entry: ret void }
- define void @load_store_v8i16(<8 x i16>* %a, <8 x i16>* %b) { entry: ret void }
- define void @load_store_v4i32(<4 x i32>* %a, <4 x i32>* %b) { entry: ret void }
- define void @load_store_v2i64(<2 x i64>* %a, <2 x i64>* %b) { entry: ret void }
- define void @load_store_v4f32(<4 x float>* %a, <4 x float>* %b) { entry: ret void }
- define void @load_store_v2f64(<2 x double>* %a, <2 x double>* %b) { entry: ret void }
-
-...
---
name: load_store_v16i8
alignment: 4
@@ -20,15 +10,16 @@ body: |
; P5600-LABEL: name: load_store_v16i8
; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
- ; P5600: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>) into %ir.a)
- ; P5600: RetRA
+ ; P5600-NEXT: {{ $}}
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>))
+ ; P5600-NEXT: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>))
+ ; P5600-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
- G_STORE %2(<16 x s8>), %0(p0) :: (store (<16 x s8>) into %ir.a)
+ %2:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>))
+ G_STORE %2(<16 x s8>), %0(p0) :: (store (<16 x s8>))
RetRA
...
@@ -42,15 +33,16 @@ body: |
; P5600-LABEL: name: load_store_v8i16
; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
- ; P5600: G_STORE [[LOAD]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>) into %ir.a)
- ; P5600: RetRA
+ ; P5600-NEXT: {{ $}}
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>))
+ ; P5600-NEXT: G_STORE [[LOAD]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>))
+ ; P5600-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
- G_STORE %2(<8 x s16>), %0(p0) :: (store (<8 x s16>) into %ir.a)
+ %2:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>))
+ G_STORE %2(<8 x s16>), %0(p0) :: (store (<8 x s16>))
RetRA
...
@@ -64,15 +56,16 @@ body: |
; P5600-LABEL: name: load_store_v4i32
; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
- ; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>) into %ir.a)
- ; P5600: RetRA
+ ; P5600-NEXT: {{ $}}
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>))
+ ; P5600-NEXT: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>))
+ ; P5600-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
- G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a)
+ %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>))
+ G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>))
RetRA
...
@@ -86,15 +79,16 @@ body: |
; P5600-LABEL: name: load_store_v2i64
; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
- ; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.a)
- ; P5600: RetRA
+ ; P5600-NEXT: {{ $}}
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>))
+ ; P5600-NEXT: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
+ ; P5600-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
- G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a)
+ %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>))
+ G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>))
RetRA
...
@@ -108,15 +102,16 @@ body: |
; P5600-LABEL: name: load_store_v4f32
; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
- ; P5600: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>) into %ir.a)
- ; P5600: RetRA
+ ; P5600-NEXT: {{ $}}
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>))
+ ; P5600-NEXT: G_STORE [[LOAD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>))
+ ; P5600-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
- G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>) into %ir.a)
+ %2:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>))
+ G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>))
RetRA
...
@@ -130,15 +125,16 @@ body: |
; P5600-LABEL: name: load_store_v2f64
; P5600: liveins: $a0, $a1
- ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
- ; P5600: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>) into %ir.a)
- ; P5600: RetRA
+ ; P5600-NEXT: {{ $}}
+ ; P5600-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; P5600-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; P5600-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>))
+ ; P5600-NEXT: G_STORE [[LOAD]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>))
+ ; P5600-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
- G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>) into %ir.a)
+ %2:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>))
+ G_STORE %2(<2 x s64>), %0(p0) :: (store (<2 x s64>))
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
index 8b9980234b841..c24beeff750ac 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir
@@ -1,13 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
---- |
-
- define void @store_i32(i32* %ptr) { entry: ret void }
- define void @store_i64(i64* %ptr) { entry: ret void }
- define void @store_float(float* %ptr) { entry: ret void }
- define void @store_double(double* %ptr) { entry: ret void }
-
-...
---
name: store_i32
alignment: 4
@@ -19,13 +11,14 @@ body: |
; MIPS32-LABEL: name: store_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32) into %ir.ptr)
- ; MIPS32: RetRA
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32))
+ ; MIPS32-NEXT: RetRA
%0:_(s32) = COPY $a0
%1:_(p0) = COPY $a1
- G_STORE %0(s32), %1(p0) :: (store (s32) into %ir.ptr)
+ G_STORE %0(s32), %1(p0) :: (store (s32))
RetRA
...
@@ -40,17 +33,18 @@ body: |
; MIPS32-LABEL: name: store_i64
; MIPS32: liveins: $a0, $a1, $a2
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
- ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32: G_STORE [[MV]](s64), [[COPY2]](p0) :: (store (s64) into %ir.ptr)
- ; MIPS32: RetRA
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+ ; MIPS32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
+ ; MIPS32-NEXT: G_STORE [[MV]](s64), [[COPY2]](p0) :: (store (s64))
+ ; MIPS32-NEXT: RetRA
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
%1:_(p0) = COPY $a2
- G_STORE %0(s64), %1(p0) :: (store (s64) into %ir.ptr)
+ G_STORE %0(s64), %1(p0) :: (store (s64))
RetRA
...
@@ -65,13 +59,14 @@ body: |
; MIPS32-LABEL: name: store_float
; MIPS32: liveins: $a1, $f12
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32) into %ir.ptr)
- ; MIPS32: RetRA
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32))
+ ; MIPS32-NEXT: RetRA
%0:_(s32) = COPY $f12
%1:_(p0) = COPY $a1
- G_STORE %0(s32), %1(p0) :: (store (s32) into %ir.ptr)
+ G_STORE %0(s32), %1(p0) :: (store (s32))
RetRA
...
@@ -86,13 +81,14 @@ body: |
; MIPS32-LABEL: name: store_double
; MIPS32: liveins: $a2, $d6
- ; MIPS32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a2
- ; MIPS32: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64) into %ir.ptr)
- ; MIPS32: RetRA
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a2
+ ; MIPS32-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64))
+ ; MIPS32-NEXT: RetRA
%0:_(s64) = COPY $d6
%1:_(p0) = COPY $a2
- G_STORE %0(s64), %1(p0) :: (store (s64) into %ir.ptr)
+ G_STORE %0(s64), %1(p0) :: (store (s64))
RetRA
...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
index 3b610859fb704..e22a44524e222 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
@@ -1,31 +1,22 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
---- |
-
- define void @load1_s8_to_load1_s32(i8* %px) {entry: ret void}
- define void @load2_s16_to_load2_s32(i16* %px) {entry: ret void}
- define void @load_store_i1(i1* %px, i1* %py) {entry: ret void}
- define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
- define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
- define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
-
-...
---
name: load1_s8_to_load1_s32
alignment: 4
tracksRegLiveness: true
body: |
- bb.1.entry:
+ bb.0:
liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_load1_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
+ ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
- %2:_(s32) = G_LOAD %0(p0) :: (load (s8) from %ir.px)
+ %2:_(s32) = G_LOAD %0(p0) :: (load (s8))
$v0 = COPY %2(s32)
RetRA implicit $v0
@@ -35,17 +26,18 @@ name: load2_s16_to_load2_s32
alignment: 4
tracksRegLiveness: true
body: |
- bb.1.entry:
+ bb.0:
liveins: $a0
; MIPS32-LABEL: name: load2_s16_to_load2_s32
; MIPS32: liveins: $a0
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16) from %ir.px)
- ; MIPS32: $v0 = COPY [[LOAD]](s32)
- ; MIPS32: RetRA implicit $v0
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; MIPS32-NEXT: $v0 = COPY [[LOAD]](s32)
+ ; MIPS32-NEXT: RetRA implicit $v0
%0:_(p0) = COPY $a0
- %2:_(s32) = G_LOAD %0(p0) :: (load (s16) from %ir.px)
+ %2:_(s32) = G_LOAD %0(p0) :: (load (s16))
$v0 = COPY %2(s32)
RetRA implicit $v0
@@ -55,23 +47,24 @@ name: load_store_i1
alignment: 4
tracksRegLiveness: true
body: |
- bb.1.entry:
+ bb.0:
liveins: $a0, $a1
; MIPS32-LABEL: name: load_store_i1
; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.py)
- ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
- ; MIPS32: G_STORE [[AND1]](s32), [[COPY]](p0) :: (store (s8) into %ir.px)
- ; MIPS32: RetRA
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s8))
+ ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
+ ; MIPS32-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
+ ; MIPS32-NEXT: G_STORE [[AND1]](s32), [[COPY]](p0) :: (store (s8))
+ ; MIPS32-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(s1) = G_LOAD %1(p0) :: (load (s1) from %ir.py)
- G_STORE %2(s1), %0(p0) :: (store (s1) into %ir.px)
+ %2:_(s1) = G_LOAD %1(p0) :: (load (s1))
+ G_STORE %2(s1), %0(p0) :: (store (s1))
RetRA
...
@@ -80,20 +73,21 @@ name: load_store_i8
alignment: 4
tracksRegLiveness: true
body: |
- bb.1.entry:
+ bb.0:
liveins: $a0, $a1
; MIPS32-LABEL: name: load_store_i8
; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.py)
- ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s8) into %ir.px)
- ; MIPS32: RetRA
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s8))
+ ; MIPS32-NEXT: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s8))
+ ; MIPS32-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(s8) = G_LOAD %1(p0) :: (load (s8) from %ir.py)
- G_STORE %2(s8), %0(p0) :: (store (s8) into %ir.px)
+ %2:_(s8) = G_LOAD %1(p0) :: (load (s8))
+ G_STORE %2(s8), %0(p0) :: (store (s8))
RetRA
...
@@ -102,20 +96,21 @@ name: load_store_i16
alignment: 4
tracksRegLiveness: true
body: |
- bb.1.entry:
+ bb.0:
liveins: $a0, $a1
; MIPS32-LABEL: name: load_store_i16
; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s16) from %ir.py)
- ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s16) into %ir.px)
- ; MIPS32: RetRA
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s16))
+ ; MIPS32-NEXT: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s16))
+ ; MIPS32-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(s16) = G_LOAD %1(p0) :: (load (s16) from %ir.py)
- G_STORE %2(s16), %0(p0) :: (store (s16) into %ir.px)
+ %2:_(s16) = G_LOAD %1(p0) :: (load (s16))
+ G_STORE %2(s16), %0(p0) :: (store (s16))
RetRA
...
@@ -124,20 +119,21 @@ name: load_store_i32
alignment: 4
tracksRegLiveness: true
body: |
- bb.1.entry:
+ bb.0:
liveins: $a0, $a1
; MIPS32-LABEL: name: load_store_i32
; MIPS32: liveins: $a0, $a1
- ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
- ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
- ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.py)
- ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s32) into %ir.px)
- ; MIPS32: RetRA
+ ; MIPS32-NEXT: {{ $}}
+ ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+ ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+ ; MIPS32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32))
+ ; MIPS32-NEXT: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s32))
+ ; MIPS32-NEXT: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
- %2:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.py)
- G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.px)
+ %2:_(s32) = G_LOAD %1(p0) :: (load (s32))
+ G_STORE %2(s32), %0(p0) :: (store (s32))
RetRA
...
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