[PATCH] D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

Mon Mar 28 15:38:54 PDT 2022

arsenm added a comment.
Herald added subscribers: StephenFan, arichardson.
Herald added a project: All.

In D76007#3310559 <https://reviews.llvm.org/D76007#3310559>, @lewis-revill wrote:

> In D76007#3308144 <https://reviews.llvm.org/D76007#3308144>, @arsenm wrote:
>
>> Register banks do not have sizes. A register bank mapping is a bank plus a size/offset that you can change based on the target's size, not part of the bank itself.
>
> Right. But before this patch there was a max size associated to the bank itself, which is queried by the verifier. And if we want to keep that concept of a maximum size surely we should have it be accurate? So for different hardware modes it should be possible for it to be different.

Why is there a maximum size concept? What is it used for? I haven't noticed thisb efore

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76007/new/

https://reviews.llvm.org/D76007