[llvm] b3e9fdd - [AArch64] Regenerate dp1.ll test, NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 24 11:33:50 PST 2022
Author: David Green
Date: 2022-02-24T19:33:45Z
New Revision: b3e9fdd17051a8d9f6357deadf39f11488cd02a9
URL: https://github.com/llvm/llvm-project/commit/b3e9fdd17051a8d9f6357deadf39f11488cd02a9
DIFF: https://github.com/llvm/llvm-project/commit/b3e9fdd17051a8d9f6357deadf39f11488cd02a9.diff
LOG: [AArch64] Regenerate dp1.ll test, NFC
The old check lines were not showing enough congtext to show issues.
Regenerate the test with theua auto-check lines to be clearer.
Added:
Modified:
llvm/test/CodeGen/AArch64/dp1.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/dp1.ll b/llvm/test/CodeGen/AArch64/dp1.ll
index 3250027c520fd..2136dd41ead0c 100644
--- a/llvm/test/CodeGen/AArch64/dp1.ll
+++ b/llvm/test/CodeGen/AArch64/dp1.ll
@@ -1,150 +1,258 @@
-; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
-; RUN: llc -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=FALLBACK,GISEL
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SDAG
+; RUN: llc -global-isel -global-isel-abort=1 -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
@var32 = global i32 0
@var64 = global i64 0
-; FALLBACK-NOT: remark{{.*}}rev_i32
define void @rev_i32() {
; CHECK-LABEL: rev_i32:
-; GISEL-LABEL: rev_i32:
- %val0_tmp = load i32, i32* @var32
- %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
-; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
-; GISEL: rev {{w[0-9]+}}, {{w[0-9]+}}
- store volatile i32 %val1_tmp, i32* @var32
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var32
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NEXT: ldr w9, [x8]
+; CHECK-NEXT: rev w9, w9
+; CHECK-NEXT: str w9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i32, i32* @var32
+ %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
+ store volatile i32 %val1_tmp, i32* @var32
+ ret void
}
-; FALLBACK-NOT: remark{{.*}}rev_i64
define void @rev_i64() {
; CHECK-LABEL: rev_i64:
-; GISEL-LABEL: rev_i64:
- %val0_tmp = load i64, i64* @var64
- %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
-; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
-; GISEL: rev {{x[0-9]+}}, {{x[0-9]+}}
- store volatile i64 %val1_tmp, i64* @var64
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var64
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NEXT: ldr x9, [x8]
+; CHECK-NEXT: rev x9, x9
+; CHECK-NEXT: str x9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i64, i64* @var64
+ %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
+ store volatile i64 %val1_tmp, i64* @var64
+ ret void
}
define void @rev32_i64() {
; CHECK-LABEL: rev32_i64:
- %val0_tmp = load i64, i64* @var64
- %val1_tmp = shl i64 %val0_tmp, 32
- %val5_tmp = sub i64 64, 32
- %val2_tmp = lshr i64 %val0_tmp, %val5_tmp
- %val3_tmp = or i64 %val1_tmp, %val2_tmp
- %val4_tmp = call i64 @llvm.bswap.i64(i64 %val3_tmp)
-; CHECK: rev32 {{x[0-9]+}}, {{x[0-9]+}}
- store volatile i64 %val4_tmp, i64* @var64
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var64
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NEXT: ldr x9, [x8]
+; CHECK-NEXT: rev32 x9, x9
+; CHECK-NEXT: str x9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i64, i64* @var64
+ %val1_tmp = shl i64 %val0_tmp, 32
+ %val5_tmp = sub i64 64, 32
+ %val2_tmp = lshr i64 %val0_tmp, %val5_tmp
+ %val3_tmp = or i64 %val1_tmp, %val2_tmp
+ %val4_tmp = call i64 @llvm.bswap.i64(i64 %val3_tmp)
+ store volatile i64 %val4_tmp, i64* @var64
+ ret void
}
define void @rev16_i32() {
; CHECK-LABEL: rev16_i32:
- %val0_tmp = load i32, i32* @var32
- %val1_tmp = shl i32 %val0_tmp, 16
- %val2_tmp = lshr i32 %val0_tmp, 16
- %val3_tmp = or i32 %val1_tmp, %val2_tmp
- %val4_tmp = call i32 @llvm.bswap.i32(i32 %val3_tmp)
-; CHECK: rev16 {{w[0-9]+}}, {{w[0-9]+}}
- store volatile i32 %val4_tmp, i32* @var32
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var32
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NEXT: ldr w9, [x8]
+; CHECK-NEXT: rev16 w9, w9
+; CHECK-NEXT: str w9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i32, i32* @var32
+ %val1_tmp = shl i32 %val0_tmp, 16
+ %val2_tmp = lshr i32 %val0_tmp, 16
+ %val3_tmp = or i32 %val1_tmp, %val2_tmp
+ %val4_tmp = call i32 @llvm.bswap.i32(i32 %val3_tmp)
+ store volatile i32 %val4_tmp, i32* @var32
+ ret void
}
define void @clz_zerodef_i32() {
; CHECK-LABEL: clz_zerodef_i32:
- %val0_tmp = load i32, i32* @var32
- %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
-; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
- store volatile i32 %val4_tmp, i32* @var32
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var32
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NEXT: ldr w9, [x8]
+; CHECK-NEXT: clz w9, w9
+; CHECK-NEXT: str w9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i32, i32* @var32
+ %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
+ store volatile i32 %val4_tmp, i32* @var32
+ ret void
}
define void @clz_zerodef_i64() {
; CHECK-LABEL: clz_zerodef_i64:
- %val0_tmp = load i64, i64* @var64
- %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
-; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
- store volatile i64 %val4_tmp, i64* @var64
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var64
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NEXT: ldr x9, [x8]
+; CHECK-NEXT: clz x9, x9
+; CHECK-NEXT: str x9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i64, i64* @var64
+ %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
+ store volatile i64 %val4_tmp, i64* @var64
+ ret void
}
define void @clz_zeroundef_i32() {
; CHECK-LABEL: clz_zeroundef_i32:
- %val0_tmp = load i32, i32* @var32
- %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
-; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
- store volatile i32 %val4_tmp, i32* @var32
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var32
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NEXT: ldr w9, [x8]
+; CHECK-NEXT: clz w9, w9
+; CHECK-NEXT: str w9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i32, i32* @var32
+ %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
+ store volatile i32 %val4_tmp, i32* @var32
+ ret void
}
define void @clz_zeroundef_i64() {
; CHECK-LABEL: clz_zeroundef_i64:
- %val0_tmp = load i64, i64* @var64
- %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
-; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
- store volatile i64 %val4_tmp, i64* @var64
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var64
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NEXT: ldr x9, [x8]
+; CHECK-NEXT: clz x9, x9
+; CHECK-NEXT: str x9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i64, i64* @var64
+ %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
+ store volatile i64 %val4_tmp, i64* @var64
+ ret void
}
define void @cttz_zerodef_i32() {
; CHECK-LABEL: cttz_zerodef_i32:
- %val0_tmp = load i32, i32* @var32
- %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
-; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
-; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
- store volatile i32 %val4_tmp, i32* @var32
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var32
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NEXT: ldr w9, [x8]
+; CHECK-NEXT: rbit w9, w9
+; CHECK-NEXT: clz w9, w9
+; CHECK-NEXT: str w9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i32, i32* @var32
+ %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
+ store volatile i32 %val4_tmp, i32* @var32
+ ret void
}
define void @cttz_zerodef_i64() {
; CHECK-LABEL: cttz_zerodef_i64:
- %val0_tmp = load i64, i64* @var64
- %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
-; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
-; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
- store volatile i64 %val4_tmp, i64* @var64
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var64
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NEXT: ldr x9, [x8]
+; CHECK-NEXT: rbit x9, x9
+; CHECK-NEXT: clz x9, x9
+; CHECK-NEXT: str x9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i64, i64* @var64
+ %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
+ store volatile i64 %val4_tmp, i64* @var64
+ ret void
}
define void @cttz_zeroundef_i32() {
; CHECK-LABEL: cttz_zeroundef_i32:
- %val0_tmp = load i32, i32* @var32
- %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
-; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
-; CHECK: clz {{w[0-9]+}}, [[REVERSED]]
- store volatile i32 %val4_tmp, i32* @var32
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var32
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NEXT: ldr w9, [x8]
+; CHECK-NEXT: rbit w9, w9
+; CHECK-NEXT: clz w9, w9
+; CHECK-NEXT: str w9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i32, i32* @var32
+ %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
+ store volatile i32 %val4_tmp, i32* @var32
+ ret void
}
define void @cttz_zeroundef_i64() {
; CHECK-LABEL: cttz_zeroundef_i64:
- %val0_tmp = load i64, i64* @var64
- %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
-; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
-; CHECK: clz {{x[0-9]+}}, [[REVERSED]]
- store volatile i64 %val4_tmp, i64* @var64
- ret void
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:var64
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NEXT: ldr x9, [x8]
+; CHECK-NEXT: rbit x9, x9
+; CHECK-NEXT: clz x9, x9
+; CHECK-NEXT: str x9, [x8]
+; CHECK-NEXT: ret
+ %val0_tmp = load i64, i64* @var64
+ %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
+ store volatile i64 %val4_tmp, i64* @var64
+ ret void
}
-; These two are just compilation tests really: the operation's set to Expand in
-; ISelLowering.
define void @ctpop_i32() {
-; CHECK-LABEL: ctpop_i32:
- %val0_tmp = load i32, i32* @var32
- %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
- store volatile i32 %val4_tmp, i32* @var32
- ret void
+; CHECK-SDAG-LABEL: ctpop_i32:
+; CHECK-SDAG: // %bb.0:
+; CHECK-SDAG-NEXT: adrp x8, :got:var32
+; CHECK-SDAG-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-SDAG-NEXT: ldr w9, [x8]
+; CHECK-SDAG-NEXT: fmov d0, x9
+; CHECK-SDAG-NEXT: cnt v0.8b, v0.8b
+; CHECK-SDAG-NEXT: uaddlv h0, v0.8b
+; CHECK-SDAG-NEXT: fmov w9, s0
+; CHECK-SDAG-NEXT: str w9, [x8]
+; CHECK-SDAG-NEXT: ret
+;
+; CHECK-GISEL-LABEL: ctpop_i32:
+; CHECK-GISEL: // %bb.0:
+; CHECK-GISEL-NEXT: adrp x8, :got:var32
+; CHECK-GISEL-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-GISEL-NEXT: ldr w9, [x8]
+; CHECK-GISEL-NEXT: fmov d0, x9
+; CHECK-GISEL-NEXT: cnt v0.8b, v0.8b
+; CHECK-GISEL-NEXT: uaddlv h0, v0.8b
+; CHECK-GISEL-NEXT: str s0, [x8]
+; CHECK-GISEL-NEXT: ret
+ %val0_tmp = load i32, i32* @var32
+ %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
+ store volatile i32 %val4_tmp, i32* @var32
+ ret void
}
define void @ctpop_i64() {
-; CHECK-LABEL: ctpop_i64:
- %val0_tmp = load i64, i64* @var64
- %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
- store volatile i64 %val4_tmp, i64* @var64
- ret void
+; CHECK-SDAG-LABEL: ctpop_i64:
+; CHECK-SDAG: // %bb.0:
+; CHECK-SDAG-NEXT: adrp x8, :got:var64
+; CHECK-SDAG-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-SDAG-NEXT: ldr d0, [x8]
+; CHECK-SDAG-NEXT: cnt v0.8b, v0.8b
+; CHECK-SDAG-NEXT: uaddlv h0, v0.8b
+; CHECK-SDAG-NEXT: fmov w9, s0
+; CHECK-SDAG-NEXT: str x9, [x8]
+; CHECK-SDAG-NEXT: ret
+;
+; CHECK-GISEL-LABEL: ctpop_i64:
+; CHECK-GISEL: // %bb.0:
+; CHECK-GISEL-NEXT: adrp x8, :got:var64
+; CHECK-GISEL-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-GISEL-NEXT: ldr x9, [x8]
+; CHECK-GISEL-NEXT: fmov d0, x9
+; CHECK-GISEL-NEXT: cnt v0.8b, v0.8b
+; CHECK-GISEL-NEXT: uaddlv h0, v0.8b
+; CHECK-GISEL-NEXT: fmov w9, s0
+; CHECK-GISEL-NEXT: mov w9, w9
+; CHECK-GISEL-NEXT: str x9, [x8]
+; CHECK-GISEL-NEXT: ret
+ %val0_tmp = load i64, i64* @var64
+ %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
+ store volatile i64 %val4_tmp, i64* @var64
+ ret void
}
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