[PATCH] D119321: [RISCV] Precommit test for D118026.

[Jianjian Guan via Phabricator via llvm-commits]

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Precommit test for D118026 <https://reviews.llvm.org/D118026>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119321

Files:
  llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll


Index: llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
+++ llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
@@ -68,6 +68,65 @@
   ret void
 }
 
+define void @foo1(i32* nocapture noundef %p1) {
+; CHECK-LABEL: foo1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi sp, sp, -192
+; CHECK-NEXT:    .cfi_def_cfa_offset 192
+; CHECK-NEXT:    sd ra, 184(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 176(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 168(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s2, 160(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    .cfi_offset s2, -32
+; CHECK-NEXT:    addi s0, sp, 192
+; CHECK-NEXT:    .cfi_def_cfa s0, 0
+; CHECK-NEXT:    andi sp, sp, -64
+; CHECK-NEXT:    mv s1, sp
+; CHECK-NEXT:    mv s2, a0
+; CHECK-NEXT:    fld ft0, 0(a0)
+; CHECK-NEXT:    fsd ft0, 56(s1) # 8-byte Folded Spill
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    addi t0, s1, 64
+; CHECK-NEXT:    li a0, 1
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    li a2, 3
+; CHECK-NEXT:    li a3, 4
+; CHECK-NEXT:    li a4, 5
+; CHECK-NEXT:    li a5, 6
+; CHECK-NEXT:    li a6, 7
+; CHECK-NEXT:    li a7, 8
+; CHECK-NEXT:    sd t0, 0(sp)
+; CHECK-NEXT:    call bar at plt
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    fld ft0, 0(s2)
+; CHECK-NEXT:    fld ft1, 56(s1) # 8-byte Folded Reload
+; CHECK-NEXT:    fadd.d ft0, ft1, ft0
+; CHECK-NEXT:    fsd ft0, 0(s2)
+; CHECK-NEXT:    addi sp, s0, -192
+; CHECK-NEXT:    ld ra, 184(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 176(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 168(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s2, 160(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 192
+; CHECK-NEXT:    ret
+entry:
+  %vla = alloca [10 x i32], align 64
+  %0 = bitcast [10 x i32]* %vla to i8*
+  call void @llvm.lifetime.start.p0i8(i64 40, i8* nonnull %0)
+  %1 = bitcast i32* %p1 to double*
+  %2 = load double, double* %1, align 32
+  %arraydecay = getelementptr inbounds [10 x i32], [10 x i32]* %vla, i64 0, i64 0
+  call void @bar(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, i32 noundef signext 7, i32 noundef signext 8, i32* noundef nonnull %arraydecay)
+  %3 = load double, double* %1, align 32
+  %add = fadd double %2, %3
+  store double %add, double* %1, align 32
+  call void @llvm.lifetime.end.p0i8(i64 40, i8* nonnull %0)
+  ret void
+}
+
 declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
 
 declare void @bar(i32 noundef signext, i32 noundef signext, i32 noundef signext, i32 noundef signext, i32 noundef signext, i32 noundef signext, i32 noundef signext, i32 noundef signext, i32* noundef)


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