[llvm] 9ee96aa - [CSKY] Add CK800 series ProcessorModel and complete related SubtargetFeatures
Zi Xuan Wu via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 8 00:03:17 PST 2022
Author: Zi Xuan Wu
Date: 2022-02-08T16:02:59+08:00
New Revision: 9ee96aaab2aa6043accf7937f8b2c9158283fa5d
URL: https://github.com/llvm/llvm-project/commit/9ee96aaab2aa6043accf7937f8b2c9158283fa5d
DIFF: https://github.com/llvm/llvm-project/commit/9ee96aaab2aa6043accf7937f8b2c9158283fa5d.diff
LOG: [CSKY] Add CK800 series ProcessorModel and complete related SubtargetFeatures
Now we only support CSKY 800 series cpus and newer cpus in the future undering CSKYv2 ABI specification.
There are 11 processor family enums for CK series cpus such as CK801, CK802, CK803, CK803S, CK804, CK805,
CK807, CK810, CK810V, CK860, CK860V.
The SchedMachineModels are not ready for different cpus, so only NoSchedModel is used.
Added:
Modified:
llvm/lib/Target/CSKY/CSKY.td
llvm/lib/Target/CSKY/CSKYSubtarget.cpp
llvm/lib/Target/CSKY/CSKYSubtarget.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td
index ddb7fe93706eb..a8db9151e127b 100644
--- a/llvm/lib/Target/CSKY/CSKY.td
+++ b/llvm/lib/Target/CSKY/CSKY.td
@@ -32,6 +32,26 @@ def HasFPUv2_DF : Predicate<"Subtarget->hasFPUv2DoubleFloat()">,
AssemblerPredicate<(all_of FeatureFPUV2_DF),
"Enable FPUv2 double float instructions">;
+def FeatureFdivdu : SubtargetFeature<"fdivdu", "HasFdivdu", "true",
+ "Enable float divide instructions">;
+def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">,
+ AssemblerPredicate<(all_of FeatureFdivdu),
+ "Enable float divide instructions">;
+
+def FeatureFPUV3_HI
+ : SubtargetFeature<"fpuv3_hi", "HasFPUv3HalfWord", "true",
+ "Enable FPUv3 harf word converting instructions">;
+def HasFPUv3_HI : Predicate<"Subtarget->hasFPUv3HalfWord()">,
+ AssemblerPredicate<(all_of FeatureFPUV3_HI),
+ "Enable FPUv3 harf word converting instructions">;
+
+def FeatureFPUV3_HF
+ : SubtargetFeature<"fpuv3_hf", "HasFPUv3HalfFloat", "true",
+ "Enable FPUv3 harf precision operate instructions">;
+def HasFPUv3_HF : Predicate<"Subtarget->hasFPUv3HalfFloat()">,
+ AssemblerPredicate<(all_of FeatureFPUV3_HF),
+ "Enable FPUv3 harf precision operate instructions">;
+
def FeatureFPUV3_SF
: SubtargetFeature<"fpuv3_sf", "HasFPUv3SingleFloat", "true",
"Enable FPUv3 single float instructions">;
@@ -46,6 +66,85 @@ def HasFPUv3_DF : Predicate<"Subtarget->hasFPUv3DoubleFloat()">,
AssemblerPredicate<(all_of FeatureFPUV3_DF),
"Enable FPUv3 double float instructions">;
+def HasFLOATE1
+ : SubtargetFeature<"floate1", "HasFLOATE1", "true", "Support CSKY floate1 instructions">;
+def iHasFLOATE1 : Predicate<"Subtarget->hasFLOATE1()">,
+ AssemblerPredicate<(all_of HasFLOATE1),
+ "Support CSKY floate1 instructions">;
+
+def HasFLOAT1E2
+ : SubtargetFeature<"float1e2", "HasFLOAT1E2", "true", "Support CSKY float1e2 instructions">;
+def iHasFLOAT1E2 : Predicate<"Subtarget->hasFLOAT1E2()">,
+ AssemblerPredicate<(all_of HasFLOAT1E2),
+ "Support CSKY float1e2 instructions">;
+
+def HasFLOAT1E3
+ : SubtargetFeature<"float1e3", "HasFLOAT1E3", "true", "Support CSKY float1e3 instructions">;
+def iHasFLOAT1E3 : Predicate<"Subtarget->hasFLOAT1E3()">,
+ AssemblerPredicate<(all_of HasFLOAT1E3),
+ "Support CSKY float1e3 instructions">;
+
+def HasFLOAT3E4
+ : SubtargetFeature<"float3e4", "HasFLOAT3E4", "true", "Support CSKY float3e4 instructions">;
+def iHasFLOAT3E4 : Predicate<"Subtarget->hasFLOAT3E4()">,
+ AssemblerPredicate<(all_of HasFLOAT3E4),
+ "Support CSKY float3e4 instructions">;
+
+def HasFLOAT7E60
+ : SubtargetFeature<"float7e60", "HasFLOAT7E60", "true", "Support CSKY float7e60 instructions">;
+def iHasFLOAT7E60 : Predicate<"Subtarget->hasFLOAT7E60()">,
+ AssemblerPredicate<(all_of HasFLOAT7E60),
+ "Support CSKY float7e60 instructions">;
+
+def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
+ "Enable divide instrutions">;
+def HasHWDiv : Predicate<"Subtarget->hasHardwareDivide()">,
+ AssemblerPredicate<(all_of FeatureHWDiv),
+ "Enable divide instrutions">;
+
+def FeatureSTM : SubtargetFeature<"multiple_stld", "HasSTM", "true",
+ "Enable multiple load/store instrutions">;
+def HasSTM : Predicate<"Subtarget->hasSTM()">,
+ AssemblerPredicate<(all_of FeatureSTM),
+ "Enable multiple load/store instrutions">;
+
+def FeaturePushPop : SubtargetFeature<"pushpop", "HasPushPop", "true",
+ "Enable push/pop instrutions">;
+def HasPushPop : Predicate<"Subtarget->hasPushPop()">,
+ AssemblerPredicate<(all_of FeaturePushPop),
+ "Enable push/pop instrutions">;
+
+def FeatureDSP
+ : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instrutions">;
+def HasDSP : Predicate<"Subtarget->hasDSP()">,
+ AssemblerPredicate<(all_of FeatureDSP),
+ "Enable DSP instrutions">;
+
+def HasDSP1E2
+ : SubtargetFeature<"dsp1e2", "HasDSP1E2", "true", "Support CSKY dsp1e2 instructions">;
+def iHasDSP1E2 : Predicate<"Subtarget->hasDSP1E2()">,
+ AssemblerPredicate<(all_of HasDSP1E2),
+ "Support CSKY dsp1e2 instructions">;
+
+def HasDSPE60
+ : SubtargetFeature<"dspe60", "HasDSPE60", "true", "Support CSKY dspe60 instructions">;
+def iHasDSPE60 : Predicate<"Subtarget->hasDSPE60()">,
+ AssemblerPredicate<(all_of HasDSPE60),
+ "Support CSKY dspe60 instructions">;
+
+def FeatureDSPV2 : SubtargetFeature<"dspv2", "HasDSPV2", "true",
+ "Enable DSP V2.0 instrutions">;
+def HasDSPV2 : Predicate<"Subtarget->hasDSPV2()">,
+ AssemblerPredicate<(all_of FeatureDSPV2),
+ "Enable DSP V2.0 instrutions">;
+
+def FeatureDSP_Silan : SubtargetFeature<"dsp_silan", "HasDSP_Silan", "true",
+ "Enable DSP Silan instrutions">;
+def HasDSP_Silan : Predicate<"Subtarget->hasDSP_Silan()">,
+ AssemblerPredicate<(all_of FeatureDSP_Silan),
+ "Enable DSP Silan instrutions">;
+
+// Atomic Support
def FeatureBTST16 : SubtargetFeature<"btst16", "HasBTST16", "true",
"Use the 16-bit btsti instruction">;
def HasBTST16 : Predicate<"Subtarget->hasBTST16()">,
@@ -59,18 +158,110 @@ def HasExtendLrw : Predicate<"Subtarget->hasExtendLrw()">,
AssemblerPredicate<(all_of FeatureExtendLrw),
"Use the extend LRW instruction">;
+def FeatureTrust : SubtargetFeature<"trust", "HasTrust", "true",
+ "Enable trust instructions">;
+def HasTrust : Predicate<"Subtarget->hasTrust()">,
+ AssemblerPredicate<(all_of FeatureTrust),
+ "Enable trust instructions">;
+
def FeatureJAVA
: SubtargetFeature<"java", "HasJAVA", "true", "Enable java instructions">;
def HasJAVA : Predicate<"Subtarget->hasJAVA()">,
AssemblerPredicate<(all_of FeatureJAVA),
"Enable java instructions">;
+def FeatureCache
+ : SubtargetFeature<"cache", "HasCache", "true", "Enable cache">;
+def HasCache : Predicate<"Subtarget->hasCache()">,
+ AssemblerPredicate<(all_of FeatureCache),
+ "Enable cache">;
+
+def FeatureNVIC
+ : SubtargetFeature<"nvic", "HasNVIC", "true", "Enable NVIC">;
+def HasNVIC : Predicate<"Subtarget->hasNVIC()">,
+ AssemblerPredicate<(all_of FeatureNVIC),
+ "Enable NVIC">;
+
def FeatureDoloop : SubtargetFeature<"doloop", "HasDoloop", "true",
"Enable doloop instructions">;
def HasDoloop : Predicate<"Subtarget->hasDoloop()">,
AssemblerPredicate<(all_of FeatureDoloop),
"Enable doloop instructions">;
+// Other features than instructions
+def FeatureHighreg : SubtargetFeature<"high-registers", "HasHighRegisters",
+ "true", "Enable r16-r31 registers">;
+def HasHighRegisters : Predicate<"Subtarget->hasHighRegisters()">,
+ AssemblerPredicate<(all_of FeatureHighreg),
+ "Enable r16-r31 registers">;
+
+def FeatureSmart : SubtargetFeature<"smart", "SmartMode", "true",
+ "Let CPU work in Smart Mode">;
+def SmartMode : Predicate<"Subtarget->smartMode()">,
+ AssemblerPredicate<(all_of FeatureSmart),
+ "Let CPU work in Smart Mode">;
+
+def FeatureVDSPV2 : SubtargetFeature<"vdspv2", "HasVDSPV2", "true",
+ "Enable vdsp-v2 instructions">;
+def HasVDSPV2 : Predicate<"Subtarget->hasVDSPV2()">,
+ AssemblerPredicate<(all_of FeatureVDSPV2),
+ "Enable vdsp-v2 instructions">;
+
+def HasVDSPV2_FLOAT : Predicate<"Subtarget->hasVDSPV2_FLOAT()">;
+def HasVDSPV2_HALF: Predicate<"Subtarget->hasVDSPV2_HALF()">;
+
+def HasVDSP2E3
+ : SubtargetFeature<"vdsp2e3", "HasVDSP2E3", "true", "Support CSKY vdsp2e3 instructions">;
+def iHasVDSP2E3 : Predicate<"Subtarget->hasVDSP2E3()">,
+ AssemblerPredicate<(all_of HasVDSP2E3),
+ "Support CSKY vdsp2e3 instructions">;
+
+def HasVDSP2E60F
+ : SubtargetFeature<"vdsp2e60f", "HasVDSP2E60F", "true", "Support CSKY vdsp2e60f instructions">;
+def iHasVDSP2E60F : Predicate<"Subtarget->hasVDSP2E60F()">,
+ AssemblerPredicate<(all_of HasVDSP2E60F),
+ "Support CSKY vdsp2e60f instructions">;
+
+def FeatureHardTP : SubtargetFeature<"hard-tp", "ReadTPHard", "true",
+ "Enable TLS Pointer register">;
+def ReadTPHard : Predicate<"Subtarget->readTPHard()">,
+ AssemblerPredicate<(all_of FeatureHardTP),
+ "Enable TLS Pointer register">;
+
+def FeatureSoftTP : SubtargetFeature<"soft-tp", "ReadTPHard", "false",
+ "Disable TLS Pointer register">;
+
+def FeatureIstack : SubtargetFeature<"istack", "EnableInterruptAttribute",
+ "true", "Enable interrput attribute">;
+def EnableInterruptAttribute
+ : Predicate<"Subtarget->enableInterruptAttribute()">,
+ AssemblerPredicate<(all_of FeatureIstack),
+ "Enable interrput attribute">;
+
+def FeatureConstPool : SubtargetFeature<"constpool", "DumpConstPool", "true",
+ "Dump the constant pool by compiler">;
+def DumpConstPool : Predicate<"Subtarget->dumpConstPool()">,
+ AssemblerPredicate<(all_of FeatureConstPool),
+ "Dump the constant pool by compiler">;
+
+def FeatureStackSize : SubtargetFeature<"stack-size", "EnableStackSize", "true",
+ "Output stack size information">;
+def EnableStackSize : Predicate<"Subtarget->enableStackSize()">,
+ AssemblerPredicate<(all_of FeatureStackSize),
+ "Output stack size information">;
+
+def FeatureCCRT
+ : SubtargetFeature<"ccrt", "UseCCRT", "true", "Use CSKY compiler runtime">;
+def UseCCRT : Predicate<"Subtarget->useCCRT()">,
+ AssemblerPredicate<(all_of FeatureCCRT),
+ "Use CSKY compiler runtime">;
+
+def FeatureVDSPV1_128 : SubtargetFeature<"vdspv1", "HasVDSPV1_128", "true",
+ "Enable 128bit vdsp-v1 instructions">;
+def HasVDSPV1_128 : Predicate<"Subtarget->hasVDSPV1_128()">,
+ AssemblerPredicate<(all_of FeatureVDSPV1_128),
+ "Enable 128bit vdsp-v1 instructions">;
+
def HasE1
: SubtargetFeature<"e1", "HasE1", "true", "Support CSKY e1 instructions",
[FeatureExtendLrw]>;
@@ -91,12 +282,25 @@ def iHas2E3 : Predicate<"Subtarget->has2E3()">,
AssemblerPredicate<(all_of Has2E3),
"Support CSKY 2e3 instructions">;
+def HasMP : SubtargetFeature<"mp", "HasMP", "true",
+ "Support CSKY mp instructions", [Has2E3]>;
+def iHasMP : Predicate<"Subtarget->hasMP()">,
+ AssemblerPredicate<(all_of HasMP),
+ "Support CSKY mp instructions">;
+
def Has3E3r1 : SubtargetFeature<"3e3r1", "Has3E3r1", "true",
"Support CSKY 3e3r1 instructions">;
def iHas3E3r1 : Predicate<"Subtarget->has3E3r1()">,
AssemblerPredicate<(all_of Has3E3r1),
"Support CSKY 3e3r1 instructions">;
+def Has3r1E3r2 : SubtargetFeature<"3e3r2", "Has3r1E3r2", "true",
+ "Support CSKY 3e3r2 instructions",
+ [Has3E3r1, FeatureDoloop]>;
+def iHas3r1E3r2 : Predicate<"Subtarget->has3r1E3r2()">,
+ AssemblerPredicate<(all_of Has3r1E3r2),
+ "Support CSKY 3e3r2 instructions">;
+
def Has3r2E3r3
: SubtargetFeature<"3e3r3", "Has3r2E3r3", "true",
"Support CSKY 3e3r3 instructions", [FeatureDoloop]>;
@@ -128,6 +332,35 @@ def iHas10E60 : Predicate<"Subtarget->has10E60()">,
AssemblerPredicate<(all_of Has10E60),
"Support CSKY 10e60 instructions">;
+//===----------------------------------------------------------------------===//
+// CSKY Processor subtarget features.
+//===----------------------------------------------------------------------===//
+
+def ProcCK801 : SubtargetFeature<"ck801", "CSKYProcFamily", "CK801",
+ "CSKY ck801 processors", []>;
+def isCK801 : Predicate<"Subtarget->isCK801()">,
+ AssemblerPredicate<(all_of ProcCK801)>;
+def ProcCK802 : SubtargetFeature<"ck802", "CSKYProcFamily", "CK802",
+ "CSKY ck802 processors", []>;
+def ProcCK803 : SubtargetFeature<"ck803", "CSKYProcFamily", "CK803",
+ "CSKY ck803 processors", []>;
+def ProcCK803S : SubtargetFeature<"ck803s", "CSKYProcFamily", "CK803S",
+ "CSKY ck803s processors", []>;
+def ProcCK804 : SubtargetFeature<"ck804", "CSKYProcFamily", "CK804",
+ "CSKY ck804 processors", []>;
+def ProcCK805 : SubtargetFeature<"ck805", "CSKYProcFamily", "CK805",
+ "CSKY ck805 processors", []>;
+def ProcCK807 : SubtargetFeature<"ck807", "CSKYProcFamily", "CK807",
+ "CSKY ck807 processors", []>;
+def ProcCK810 : SubtargetFeature<"ck810", "CSKYProcFamily", "CK810",
+ "CSKY ck810 processors", []>;
+def ProcCK810V : SubtargetFeature<"ck810v", "CSKYProcFamily", "CK810V",
+ "CSKY ck810v processors", []>;
+def ProcCK860 : SubtargetFeature<"ck860", "CSKYProcFamily", "CK860",
+ "CSKY ck860 processors", []>;
+def ProcCK860V : SubtargetFeature<"ck860v", "CSKYProcFamily", "CK860V",
+ "CSKY ck860v processors", []>;
+
//===----------------------------------------------------------------------===//
// Registers, calling conventions, instruction descriptions.
//===----------------------------------------------------------------------===//
@@ -142,6 +375,296 @@ include "CSKYInstrInfo.td"
def : ProcessorModel<"generic", NoSchedModel, []>;
+// CK801 series
+class CK801<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : ProcessorModel<n, m, !listconcat(f, [HasE1, FeatureTrust, FeatureBTST16, ProcCK801]), !listconcat(tunef, [])>;
+
+def : CK801<"ck801", NoSchedModel, []>;
+def : CK801<"ck801t", NoSchedModel, []>;
+def : CK801<"e801", NoSchedModel, []>;
+
+// CK802 series
+class CK802<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : ProcessorModel<n, m, !listconcat(f, [HasE2, FeatureTrust, FeatureBTST16, FeatureNVIC, ProcCK802]), !listconcat(tunef, [])>;
+
+def : CK802<"ck802", NoSchedModel, []>;
+def : CK802<"ck802t", NoSchedModel, []>;
+def : CK802<"ck802j", NoSchedModel, [FeatureJAVA]>;
+def : CK802<"e802", NoSchedModel, []>;
+def : CK802<"e802t", NoSchedModel, []>;
+def : CK802<"s802", NoSchedModel, []>;
+def : CK802<"s802t", NoSchedModel, []>;
+
+// CK803 series
+class CK803<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : ProcessorModel<n, m, !listconcat(f, [Has2E3, HasMP, FeatureTrust, FeatureBTST16, FeatureNVIC, FeatureHWDiv, ProcCK803]), !listconcat(tunef, [])>;
+
+def : CK803<"ck803", NoSchedModel, []>;
+def : CK803<"ck803h", NoSchedModel, []>;
+def : CK803<"ck803t", NoSchedModel, []>;
+def : CK803<"ck803ht", NoSchedModel, []>;
+def : CK803<"ck803f", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803fh", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803e", NoSchedModel, [FeatureDSP, HasDSP1E2, HasDSPE60]>;
+def : CK803<"ck803eh", NoSchedModel, [FeatureDSP, HasDSP1E2, HasDSPE60]>;
+def : CK803<"ck803et", NoSchedModel, [FeatureDSP, HasDSP1E2, HasDSPE60]>;
+def : CK803<"ck803eht", NoSchedModel, [FeatureDSP, HasDSP1E2, HasDSPE60]>;
+def : CK803<"ck803ef", NoSchedModel,
+ [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803efh", NoSchedModel,
+ [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803ft", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803eft", NoSchedModel,
+ [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803efht", NoSchedModel,
+ [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803r1", NoSchedModel, [Has3E3r1, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803hr1", NoSchedModel, [Has3E3r1, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803tr1", NoSchedModel, [Has3E3r1, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803htr1", NoSchedModel, [Has3E3r1, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803fr1", NoSchedModel,
+ [Has3E3r1, Has3r2E3r3, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureDSPV2]>;
+def : CK803<"ck803fhr1", NoSchedModel,
+ [Has3E3r1, Has3r2E3r3, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureDSPV2]>;
+def : CK803<"ck803er1", NoSchedModel,
+ [Has3E3r1, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803etr1", NoSchedModel,
+ [Has3E3r1, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803ehr1", NoSchedModel,
+ [Has3E3r1, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803ehtr1", NoSchedModel,
+ [Has3E3r1, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803efr1", NoSchedModel,
+ [Has3E3r1, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803efhr1", NoSchedModel,
+ [Has3E3r1, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803ftr1", NoSchedModel, [Has3E3r1, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureDSPV2]>;
+def : CK803<"ck803eftr1", NoSchedModel,
+ [Has3E3r1, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803efhtr1", NoSchedModel,
+ [Has3E3r1, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803r2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803hr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803tr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803htr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803fr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803fhr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803er2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803etr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803ehr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803ehtr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803efr2", NoSchedModel,
+ [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803efhr2", NoSchedModel,
+ [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803ftr2", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803eftr2", NoSchedModel,
+ [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803efhtr2", NoSchedModel,
+ [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803r3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803hr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803tr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803htr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2]>;
+def : CK803<"ck803fr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803fhr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803er3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803etr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803ehr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803ehtr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureHighreg]>;
+def : CK803<"ck803efr3", NoSchedModel,
+ [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803efhr3", NoSchedModel,
+ [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803ftr3", NoSchedModel, [Has3r1E3r2, Has3r2E3r3, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803<"ck803eftr3", NoSchedModel,
+ [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"ck803efhtr3", NoSchedModel,
+ [Has3r1E3r2, Has3r2E3r3, FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK803<"s803", NoSchedModel, [Has3r1E3r2, Has3r2E3r3]>;
+def : CK803<"s803t", NoSchedModel, [Has3r1E3r2, Has3r2E3r3]>;
+def : CK803<"e803", NoSchedModel, [Has3r1E3r2, Has3r2E3r3]>;
+def : CK803<"e803t", NoSchedModel, [Has3r1E3r2, Has3r2E3r3]>;
+
+// CK803S series
+class CK803S<string n, SchedMachineModel m, list<SubtargetFeature> f,
+list<SubtargetFeature> tunef = []> : CK803<n, m, !listconcat(f, [Has3E3r1, ProcCK803S]), tunef>;
+
+def : CK803S<"ck803s", NoSchedModel, []>;
+def : CK803S<"ck803sn", NoSchedModel, [FeatureDSP_Silan]>;
+def : CK803S<"ck803st", NoSchedModel, []>;
+def : CK803S<"ck803snt", NoSchedModel, [FeatureDSP_Silan]>;
+def : CK803S<"ck803sf", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803S<"ck803sfn", NoSchedModel, [FeatureFPUV2_SF, FeatureDSP_Silan, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803S<"ck803se", NoSchedModel, [FeatureDSP, HasDSP1E2, HasDSPE60]>;
+def : CK803S<"ck803sen", NoSchedModel, [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureDSP_Silan]>;
+def : CK803S<"ck803sef", NoSchedModel,
+ [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803S<"ck803sefn", NoSchedModel,
+ [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, FeatureDSP_Silan,
+ HasFLOATE1, HasFLOAT1E3]>;
+def : CK803S<"ck803seft", NoSchedModel,
+ [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK803S<"ck803sefnt", NoSchedModel,
+ [FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, FeatureDSP_Silan,
+ HasFLOATE1, HasFLOAT1E3]>;
+
+// CK804 series
+class CK804<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : CK803<n, m, !listconcat(f, [Has3r1E3r2, Has3r2E3r3, ProcCK804]), !listconcat(tunef, [])>;
+
+def : CK804<"ck804", NoSchedModel, []>;
+def : CK804<"ck804h", NoSchedModel, []>;
+def : CK804<"ck804t", NoSchedModel, []>;
+def : CK804<"ck804ht", NoSchedModel, []>;
+def : CK804<"ck804f", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK804<"ck804fh", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK804<"ck804e", NoSchedModel, [FeatureDSPV2, FeatureHighreg]>;
+def : CK804<"ck804et", NoSchedModel, [FeatureDSPV2, FeatureHighreg]>;
+def : CK804<"ck804eh", NoSchedModel, [FeatureDSPV2, FeatureHighreg]>;
+def : CK804<"ck804eht", NoSchedModel, [FeatureDSPV2, FeatureHighreg]>;
+def : CK804<"ck804ef", NoSchedModel, [FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK804<"ck804efh", NoSchedModel, [FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK804<"ck804ft", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK804<"ck804eft", NoSchedModel, [FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK804<"ck804efht", NoSchedModel, [FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK804<"e804d", NoSchedModel, [FeatureDSPV2, FeatureHighreg]>;
+def : CK804<"e804dt", NoSchedModel, [FeatureDSPV2, FeatureHighreg]>;
+def : CK804<"e804f", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK804<"e804ft", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK804<"e804df", NoSchedModel, [FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+def : CK804<"e804dft", NoSchedModel, [FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3, FeatureHighreg]>;
+
+// CK805 series
+class CK805<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : CK803<n, m, !listconcat(f, [FeatureHighreg, FeatureVDSPV2, HasVDSP2E3, Has3r1E3r2, Has3r2E3r3, ProcCK805]),
+ !listconcat(tunef, [])>;
+
+def : CK805<"ck805", NoSchedModel, []>;
+def : CK805<"i805", NoSchedModel, []>;
+def : CK805<"ck805t", NoSchedModel, []>;
+def : CK805<"i805f", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK805<"ck805f", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK805<"ck805e", NoSchedModel, [FeatureDSPV2]>;
+def : CK805<"ck805ef", NoSchedModel, [FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK805<"ck805et", NoSchedModel, [FeatureDSPV2]>;
+def : CK805<"ck805ft", NoSchedModel, [FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+def : CK805<"ck805eft", NoSchedModel, [FeatureDSPV2, FeatureFPUV2_SF, HasFLOATE1, HasFLOAT1E3]>;
+
+// CK807 series
+class CK807<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : ProcessorModel<n, m, !listconcat(f,
+ [ Has3E7, HasMP, HasMP1E2, FeatureTrust, FeatureHWDiv, FeatureDSP, HasDSP1E2, HasDSPE60,
+ FeatureHighreg, FeatureHardTP, FeatureNVIC, FeatureCache, ProcCK807]), !listconcat(tunef, [])>;
+
+def : CK807<"ck807", NoSchedModel, []>;
+def : CK807<"c807", NoSchedModel, []>;
+def : CK807<"r807", NoSchedModel, []>;
+def : CK807<"ck807e", NoSchedModel, [FeatureDSP, HasDSP1E2, HasDSPE60]>;
+def : CK807<"ck807f", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2, HasFLOAT1E3, HasFLOAT3E4]>;
+def : CK807<"c807f", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2, HasFLOAT1E3, HasFLOAT3E4]>;
+def : CK807<"r807f", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2, HasFLOAT1E3, HasFLOAT3E4]>;
+def : CK807<"ck807ef", NoSchedModel, [
+ FeatureDSP, HasDSP1E2, HasDSPE60, FeatureFPUV2_SF, FeatureFPUV2_DF,
+ FeatureFdivdu, HasFLOATE1, HasFLOAT1E2, HasFLOAT1E3, HasFLOAT3E4]>;
+
+// CK810 series
+class CK810<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : ProcessorModel<n, m, !listconcat(f,
+ [ Has7E10, HasMP, HasMP1E2, FeatureTrust, FeatureHWDiv, FeatureDSP, HasDSP1E2, HasDSPE60,
+ FeatureHighreg, FeatureHardTP, FeatureNVIC, FeatureCache, ProcCK810]), !listconcat(tunef, [])>;
+
+def : CK810<"ck810", NoSchedModel, []>;
+def : CK810<"ck810e", NoSchedModel, []>;
+def : CK810<"ck810t", NoSchedModel, []>;
+def : CK810<"ck810et", NoSchedModel, []>;
+def : CK810<"c810", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2]>;
+def : CK810<"ck810f", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2]>;
+def : CK810<"ck810ef", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2]>;
+def : CK810<"ck810ft", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2]>;
+def : CK810<"ck810eft", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2]>;
+def : CK810<"c810t", NoSchedModel,
+ [FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2]>;
+
+class CK810V<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : CK810<n, m, !listconcat(f, [FeatureVDSPV1_128, ProcCK810V]), !listconcat(tunef, [])>;
+
+def : CK810V<"ck810v", NoSchedModel, []>;
+def : CK810V<"ck810ev", NoSchedModel, []>;
+def : CK810V<"ck810tv", NoSchedModel, []>;
+def : CK810V<"ck810etv", NoSchedModel, []>;
+def : CK810V<"ck810fv", NoSchedModel, [
+ FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2
+]>;
+def : CK810V<"ck810efv", NoSchedModel, [
+ FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2
+]>;
+def : CK810V<"c810v", NoSchedModel, [
+ FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2
+]>;
+def : CK810V<"ck810ftv", NoSchedModel, [
+ FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2
+]>;
+def : CK810V<"ck810eftv", NoSchedModel, [
+ FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2
+]>;
+def : CK810V<"c810tv", NoSchedModel, [
+ FeatureFPUV2_SF, FeatureFPUV2_DF, FeatureFdivdu,
+ HasFLOATE1, HasFLOAT1E2
+]>;
+
+// CK860 series
+class CK860<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : ProcessorModel<n, m, !listconcat(f,
+ [ Has10E60, HasMP, HasMP1E2, Has3r1E3r2, Has3r2E3r3, FeatureTrust, FeatureBTST16, FeatureHWDiv, HasDSPE60,
+ FeatureHighreg, FeatureHardTP, FeatureNVIC, FeatureCache, ProcCK860]), !listconcat(tunef, [])>;
+
+class CK860V<string n, SchedMachineModel m, list<SubtargetFeature> f,
+ list<SubtargetFeature> tunef = []>
+ : CK860<n, m, !listconcat(f, [FeatureVDSPV2, HasVDSP2E60F, ProcCK860V]), !listconcat(tunef, [])>;
+
+def : CK860<"ck860", NoSchedModel, []>;
+def : CK860<"ck860f", NoSchedModel,
+ [FeatureFPUV3_HI, FeatureFPUV3_HF, FeatureFPUV3_SF, FeatureFPUV3_DF, HasFLOAT7E60]>;
+def : CK860<"c860", NoSchedModel,
+ [FeatureFPUV3_HI, FeatureFPUV3_HF, FeatureFPUV3_SF, FeatureFPUV3_DF, HasFLOAT7E60]>;
+def : CK860V<"c860v", NoSchedModel,
+ [FeatureFPUV3_HI, FeatureFPUV3_HF, FeatureFPUV3_SF, FeatureFPUV3_DF, HasFLOAT7E60]>;
+def : CK860V<"ck860v", NoSchedModel, []>;
+def : CK860V<"ck860fv", NoSchedModel,
+ [FeatureFPUV3_HI, FeatureFPUV3_HF, FeatureFPUV3_SF, FeatureFPUV3_DF, HasFLOAT7E60]>;
+
//===----------------------------------------------------------------------===//
// Define the CSKY target.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/CSKY/CSKYSubtarget.cpp b/llvm/lib/Target/CSKY/CSKYSubtarget.cpp
index 963c2ede9c441..3015db131f951 100644
--- a/llvm/lib/Target/CSKY/CSKYSubtarget.cpp
+++ b/llvm/lib/Target/CSKY/CSKYSubtarget.cpp
@@ -33,14 +33,42 @@ CSKYSubtarget &CSKYSubtarget::initializeSubtargetDependencies(
UseHardFloatABI = false;
HasFPUv2SingleFloat = false;
HasFPUv2DoubleFloat = false;
+ HasFPUv3HalfWord = false;
+ HasFPUv3HalfFloat = false;
HasFPUv3SingleFloat = false;
HasFPUv3DoubleFloat = false;
-
+ HasFdivdu = false;
+ HasFLOATE1 = false;
+ HasFLOAT1E2 = false;
+ HasFLOAT1E3 = false;
+ HasFLOAT3E4 = false;
+ HasFLOAT7E60 = false;
+ HasExtendLrw = false;
HasBTST16 = false;
+ HasTrust = false;
HasJAVA = false;
- HasExtendLrw = false;
+ HasCache = false;
+ HasNVIC = false;
+ HasDSP = false;
+ HasDSP1E2 = false;
+ HasDSPE60 = false;
+ HasDSPV2 = false;
+ HasDSP_Silan = false;
HasDoloop = false;
+ HasHardwareDivide = false;
HasHighRegisters = false;
+ HasVDSPV2 = false;
+ HasVDSP2E3 = false;
+ HasVDSP2E60F = false;
+ ReadTPHard = false;
+ HasVDSPV1_128 = false;
+ UseCCRT = false;
+ DumpConstPool = false;
+ EnableInterruptAttribute = false;
+ HasPushPop = false;
+ HasSTM = false;
+ SmartMode = false;
+ EnableStackSize = false;
HasE1 = false;
HasE2 = false;
diff --git a/llvm/lib/Target/CSKY/CSKYSubtarget.h b/llvm/lib/Target/CSKY/CSKYSubtarget.h
index 4cd590e8e76e6..9e7ad00c0a504 100644
--- a/llvm/lib/Target/CSKY/CSKYSubtarget.h
+++ b/llvm/lib/Target/CSKY/CSKYSubtarget.h
@@ -36,18 +36,65 @@ class CSKYSubtarget : public CSKYGenSubtargetInfo {
CSKYTargetLowering TLInfo;
SelectionDAGTargetInfo TSInfo;
+ enum CSKYProcFamilyEnum {
+ Others,
+
+ CK801,
+ CK802,
+ CK803,
+ CK803S,
+ CK804,
+ CK805,
+ CK807,
+ CK810,
+ CK810V,
+ CK860,
+ CK860V
+ };
+
+ /// CSKYProcFamily - CSKY processor family: CK801, CK802, and others.
+ CSKYProcFamilyEnum CSKYProcFamily = Others;
+
bool UseHardFloat;
bool UseHardFloatABI;
bool HasFPUv2SingleFloat;
bool HasFPUv2DoubleFloat;
+ bool HasFPUv3HalfWord;
+ bool HasFPUv3HalfFloat;
bool HasFPUv3SingleFloat;
bool HasFPUv3DoubleFloat;
-
+ bool HasFdivdu;
+ bool HasFLOATE1;
+ bool HasFLOAT1E2;
+ bool HasFLOAT1E3;
+ bool HasFLOAT3E4;
+ bool HasFLOAT7E60;
bool HasBTST16;
- bool HasJAVA;
bool HasExtendLrw;
+ bool HasTrust;
+ bool HasJAVA;
+ bool HasCache;
+ bool HasNVIC;
+ bool HasDSP;
+ bool HasDSP1E2;
+ bool HasDSPE60;
+ bool HasDSPV2;
+ bool HasDSP_Silan;
bool HasDoloop;
+ bool HasHardwareDivide;
bool HasHighRegisters;
+ bool HasVDSPV2;
+ bool HasVDSP2E3;
+ bool HasVDSP2E60F;
+ bool ReadTPHard;
+ bool HasVDSPV1_128;
+ bool UseCCRT;
+ bool DumpConstPool;
+ bool EnableInterruptAttribute;
+ bool HasPushPop;
+ bool HasSTM;
+ bool SmartMode;
+ bool EnableStackSize;
bool HasE1;
bool HasE2;
@@ -92,16 +139,49 @@ class CSKYSubtarget : public CSKYGenSubtargetInfo {
bool hasFPUv2SingleFloat() const { return HasFPUv2SingleFloat; }
bool hasFPUv2DoubleFloat() const { return HasFPUv2DoubleFloat; }
bool hasFPUv2() const { return HasFPUv2SingleFloat || HasFPUv2DoubleFloat; }
+ bool hasFPUv3HalfWord() const { return HasFPUv3HalfWord; }
+ bool hasFPUv3HalfFloat() const { return HasFPUv3HalfFloat; }
bool hasFPUv3SingleFloat() const { return HasFPUv3SingleFloat; }
bool hasFPUv3DoubleFloat() const { return HasFPUv3DoubleFloat; }
- bool hasFPUv3() const { return HasFPUv3SingleFloat || HasFPUv3DoubleFloat; }
+ bool hasFPUv3() const {
+ return HasFPUv3HalfFloat || HasFPUv3SingleFloat || HasFPUv3DoubleFloat;
+ }
bool hasAnyFloatExt() const { return hasFPUv2() || hasFPUv3(); };
-
+ bool hasFdivdu() const { return HasFdivdu; }
+ bool hasFLOATE1() const { return HasFLOATE1; }
+ bool hasFLOAT1E2() const { return HasFLOAT1E2; }
+ bool hasFLOAT1E3() const { return HasFLOAT1E3; }
+ bool hasFLOAT3E4() const { return HasFLOAT3E4; }
+ bool hasFLOAT7E60() const { return HasFLOAT7E60; }
+ bool hasExtendLrw() const { return HasExtendLrw; }
bool hasBTST16() const { return HasBTST16; }
+ bool hasTrust() const { return HasTrust; }
bool hasJAVA() const { return HasJAVA; }
- bool hasExtendLrw() const { return HasExtendLrw; }
+ bool hasCache() const { return HasCache; }
+ bool hasNVIC() const { return HasNVIC; }
+ bool hasDSP() const { return HasDSP; }
+ bool hasDSP1E2() const { return HasDSP1E2; }
+ bool hasDSPE60() const { return HasDSPE60; }
+ bool hasDSPV2() const { return HasDSPV2; }
+ bool hasDSP_Silan() const { return HasDSP_Silan; }
bool hasDoloop() const { return HasDoloop; }
bool hasHighRegisters() const { return HasHighRegisters; }
+ bool hasVDSPV2() const { return HasVDSPV2; }
+ bool hasVDSPV2_FLOAT() const { return HasVDSPV2 && UseHardFloat; }
+ bool hasVDSPV2_HALF() const {
+ return HasVDSPV2 && UseHardFloat && HasFPUv3HalfFloat;
+ }
+ bool hasVDSP2E3() const { return HasVDSP2E3; }
+ bool hasVDSP2E60F() const { return HasVDSP2E60F; }
+ bool readTPHard() const { return ReadTPHard; }
+ bool hasVDSPV1_128() const { return HasVDSPV1_128; }
+ bool useCCRT() const { return UseCCRT; }
+ bool dumpConstPool() const { return DumpConstPool; }
+ bool enableInterruptAttribute() const { return EnableInterruptAttribute; }
+ bool hasPushPop() const { return HasPushPop; }
+ bool hasSTM() const { return HasSTM; }
+ bool smartMode() const { return SmartMode; }
+ bool enableStackSize() const { return EnableStackSize; }
bool hasE1() const { return HasE1; }
bool hasE2() const { return HasE2; }
@@ -114,6 +194,18 @@ class CSKYSubtarget : public CSKYGenSubtargetInfo {
bool hasMP1E2() const { return HasMP1E2; }
bool has7E10() const { return Has7E10; }
bool has10E60() const { return Has10E60; }
+
+ bool isCK801() const { return CSKYProcFamily == CK801; }
+ bool isCK802() const { return CSKYProcFamily == CK802; }
+ bool isCK803() const { return CSKYProcFamily == CK803; }
+ bool isCK803S() const { return CSKYProcFamily == CK803S; }
+ bool isCK804() const { return CSKYProcFamily == CK804; }
+ bool isCK805() const { return CSKYProcFamily == CK805; }
+ bool isCK807() const { return CSKYProcFamily == CK807; }
+ bool isCK810() const { return CSKYProcFamily == CK810; }
+ bool isCK810V() const { return CSKYProcFamily == CK810V; }
+ bool isCK860() const { return CSKYProcFamily == CK860; }
+ bool isCK860V() const { return CSKYProcFamily == CK860V; }
};
} // namespace llvm
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