[llvm] 73ac3b1 - [VE] Packed v512i32 isel and tests
Simon Moll via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 3 02:02:59 PST 2022
Author: Simon Moll
Date: 2022-02-03T11:01:54+01:00
New Revision: 73ac3b137101594663aad9901598dfa1aced9c78
URL: https://github.com/llvm/llvm-project/commit/73ac3b137101594663aad9901598dfa1aced9c78
DIFF: https://github.com/llvm/llvm-project/commit/73ac3b137101594663aad9901598dfa1aced9c78.diff
LOG: [VE] Packed v512i32 isel and tests
Reviewed By: kaz7
Differential Revision: https://reviews.llvm.org/D118332
Added:
llvm/test/CodeGen/VE/Packed/vp_add.ll
llvm/test/CodeGen/VE/Packed/vp_and.ll
llvm/test/CodeGen/VE/Packed/vp_or.ll
llvm/test/CodeGen/VE/Packed/vp_shl.ll
llvm/test/CodeGen/VE/Packed/vp_sra.ll
llvm/test/CodeGen/VE/Packed/vp_srl.ll
llvm/test/CodeGen/VE/Packed/vp_sub.ll
llvm/test/CodeGen/VE/Packed/vp_xor.ll
Modified:
llvm/lib/Target/VE/VVPInstrPatternsVec.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VVPInstrPatternsVec.td b/llvm/lib/Target/VE/VVPInstrPatternsVec.td
index bba56fa50e8cb..cd39e56bb3715 100644
--- a/llvm/lib/Target/VE/VVPInstrPatternsVec.td
+++ b/llvm/lib/Target/VE/VVPInstrPatternsVec.td
@@ -237,6 +237,24 @@ defm : Binary_rv_vr_vv_ShortLong<vvp_fdiv,
f64, v256f64, "VFDIVD",
f32, v256f32, "VFDIVS">;
+defm : Binary_rv_vv<c_vvp_and,
+ i64, v512i32, v512i1, "PVAND">;
+defm : Binary_rv_vv<c_vvp_or,
+ i64, v512i32, v512i1, "PVOR">;
+defm : Binary_rv_vv<c_vvp_xor,
+ i64, v512i32, v512i1, "PVXOR">;
+
+defm : Binary_rv_vv<c_vvp_add,
+ i64, v512i32, v512i1, "PVADDU">;
+defm : Binary_rv_vv<vvp_sub,
+ i64, v512i32, v512i1, "PVSUBU">;
+defm : Binary_vr_vv<vvp_srl,
+ i64, v512i32, v512i1, "PVSRL">;
+defm : Binary_vr_vv<vvp_sra,
+ i64, v512i32, v512i1, "PVSRA">;
+defm : Binary_vr_vv<vvp_shl,
+ i64, v512i32, v512i1, "PVSLL">;
+
defm : Binary_rv_vv<c_vvp_fadd,
i64, v512f32, v512i1, "PVFADD">;
defm : Binary_rv_vv<c_vvp_fmul,
diff --git a/llvm/test/CodeGen/VE/Packed/vp_add.ll b/llvm/test/CodeGen/VE/Packed/vp_add.ll
new file mode 100644
index 0000000000000..7942cf45cf44c
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_add.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x i32> @llvm.vp.add.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
+
+define fastcc <512 x i32> @test_vp_add_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_add_v512i32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvaddu %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_add_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_add_v512i32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvaddu %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
+ %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_add_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_add_v512i32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvaddu %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
+ %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.add.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_and.ll b/llvm/test/CodeGen/VE/Packed/vp_and.ll
new file mode 100644
index 0000000000000..8f47837c71e93
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_and.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x i32> @llvm.vp.and.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
+
+define fastcc <512 x i32> @test_vp_and_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_and_v512i32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvand %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_and_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_and_v512i32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvand %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
+ %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_and_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_and_v512i32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvand %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
+ %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.and.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_or.ll b/llvm/test/CodeGen/VE/Packed/vp_or.ll
new file mode 100644
index 0000000000000..186b70f772d2f
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_or.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x i32> @llvm.vp.or.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
+
+define fastcc <512 x i32> @test_vp_or_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_or_v512i32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvor %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_or_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_or_v512i32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvor %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
+ %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_or_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_or_v512i32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvor %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
+ %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.or.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_shl.ll b/llvm/test/CodeGen/VE/Packed/vp_shl.ll
new file mode 100644
index 0000000000000..3e11d4bdcc655
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_shl.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x i32> @llvm.vp.shl.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
+
+define fastcc <512 x i32> @test_vp_shl_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_shl_v512i32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvsll %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_shl_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_shl_v512i32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: lea %s2, 256
+; CHECK-NEXT: lvl %s2
+; CHECK-NEXT: vbrd %v1, %s0
+; CHECK-NEXT: adds.w.sx %s0, 1, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvsll %v0, %v1, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
+ %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_shl_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_shl_v512i32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvsll %v0, %v0, %s0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
+ %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.shl.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_sra.ll b/llvm/test/CodeGen/VE/Packed/vp_sra.ll
new file mode 100644
index 0000000000000..1b58a2f89c6ef
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_sra.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
+
+define fastcc <512 x i32> @test_vp_ashr_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_ashr_v512i32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvsra %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_ashr_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_ashr_v512i32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: lea %s2, 256
+; CHECK-NEXT: lvl %s2
+; CHECK-NEXT: vbrd %v1, %s0
+; CHECK-NEXT: adds.w.sx %s0, 1, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvsra %v0, %v1, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
+ %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_ashr_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_ashr_v512i32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvsra %v0, %v0, %s0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
+ %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_srl.ll b/llvm/test/CodeGen/VE/Packed/vp_srl.ll
new file mode 100644
index 0000000000000..116b506a8db99
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_srl.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
+
+define fastcc <512 x i32> @test_vp_lshr_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_lshr_v512i32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvsrl %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_lshr_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_lshr_v512i32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: lea %s2, 256
+; CHECK-NEXT: lvl %s2
+; CHECK-NEXT: vbrd %v1, %s0
+; CHECK-NEXT: adds.w.sx %s0, 1, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvsrl %v0, %v1, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
+ %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_lshr_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_lshr_v512i32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvsrl %v0, %v0, %s0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
+ %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_sub.ll b/llvm/test/CodeGen/VE/Packed/vp_sub.ll
new file mode 100644
index 0000000000000..e846af91af031
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_sub.ll
@@ -0,0 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x i32> @llvm.vp.sub.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
+
+define fastcc <512 x i32> @test_vp_sub_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_sub_v512i32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvsubu %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x i32> @llvm.vp.sub.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_sub_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_sub_v512i32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvsubu %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
+ %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.sub.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_sub_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_sub_v512i32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: lea %s2, 256
+; CHECK-NEXT: lvl %s2
+; CHECK-NEXT: vbrd %v1, %s0
+; CHECK-NEXT: adds.w.sx %s0, 1, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvsubu %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
+ %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.sub.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
diff --git a/llvm/test/CodeGen/VE/Packed/vp_xor.ll b/llvm/test/CodeGen/VE/Packed/vp_xor.ll
new file mode 100644
index 0000000000000..b7f1a3423d45d
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Packed/vp_xor.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+declare <512 x i32> @llvm.vp.xor.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
+
+define fastcc <512 x i32> @test_vp_xor_v512i32_vv(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_xor_v512i32_vv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: adds.w.sx %s0, 1, %s0
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 1
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvxor %v0, %v0, %v1, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %r0 = call <512 x i32> @llvm.vp.xor.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_xor_v512i32_rv(i32 %s0, <512 x i32> %i1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_xor_v512i32_rv:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvxor %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %xins = insertelement <512 x i32> undef, i32 %s0, i32 0
+ %i0 = shufflevector <512 x i32> %xins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.xor.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
+
+define fastcc <512 x i32> @test_vp_xor_v512i32_vr(<512 x i32> %i0, i32 %s1, <512 x i1> %m, i32 %n) {
+; CHECK-LABEL: test_vp_xor_v512i32_vr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: sll %s2, %s0, 32
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: or %s0, %s0, %s2
+; CHECK-NEXT: adds.w.sx %s1, 1, %s1
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: srl %s1, %s1, 1
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pvxor %v0, %s0, %v0, %vm2
+; CHECK-NEXT: b.l.t (, %s10)
+ %yins = insertelement <512 x i32> undef, i32 %s1, i32 0
+ %i1 = shufflevector <512 x i32> %yins, <512 x i32> undef, <512 x i32> zeroinitializer
+ %r0 = call <512 x i32> @llvm.vp.xor.v512i32(<512 x i32> %i0, <512 x i32> %i1, <512 x i1> %m, i32 %n)
+ ret <512 x i32> %r0
+}
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